Job Description

Job Summary

Experience: 5+ years

Own full-chip STA signoff for all PVT corners and modes (functional, scan, low-power, etc.)

Drive timing closure at chip level, including setup/hold, noise, OCV/AOCV/POCV

Analyze and resolve timing violations across hierarchical boundaries

🔹 Constraint Management

Define and validate SDC constraints for chip-level integration

Ensure proper timing budgeting and partitioning across blocks

Review and align block-level constraints with chip-level requirements

🔹 Signoff & Methodology

Lead signoff STA using tools like:

Synopsys PrimeTime

Cadence Tempus

Implement and improve:

MCMM (Multi-Corner Multi-Mode) flows

SI-aware analysis (crosstalk, noise)

ECO strategies for timing closure

Ensure timing correlation between block and top level

🔹 Debug & Optimization

Perform deep analysis on:

Critical paths

False/multicycle paths

Clock domain crossings (CDC timing perspective)

Drive timing ECOs with minimal impact on power/area

🔸Strong expertise in:

STA fundamentals (setup/hold, skew, jitter, latency)

OCV/AOCV/POCV concepts

SI effects and derates

Hands-on experience with:

Synopsys PrimeTime / Cadence Tempus

Deep understanding of:

Clock tree design and analysis

Low power (UPF/CPF) impact on timing

Advanced nodes (7nm, 5nm preferred)

Experience in hierarchical STA flows

Exposure to automation (TCL/Python scripting)

Knowledge of EM/IR and physical effects on timing

Experience working with global teams / customers

Zero/near-zero timing violations at tapeout

Clean signoff across all modes/corners

Predictable timing closure cycles

Strong correlation between block and top-level timing

Key Responsibilities

1. To leverage design expertise to ensure that software and products exhibit user-friendliness, intuitiveness, and alignment with user expectations, contributing to the creation of seamless user experiences.
2. To lead a team of designers, provide guidance, and ensuring the delivery of high-quality design solutions in alignment with the overall business goals.
3. To present design concepts and play a crucial role in shaping the overall design vision and strategy.
4. To stay abreast of industry trends, emerging technologies to drive innovation and excellence in design.

Skill Requirements

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Other Requirements

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