Job Description

• Lead development of iJTAG (IEEE 1687) based test solutions, including scan network modeling, instrument access, and test pattern execution.
  • Design and implement DFT methodologies including scan, BIST, and hierarchical access mechanisms.
  • Build AI/ML features in DFT tools for pattern compaction, failure prediction, and scan-failure root-cause analysis
  • Develop scalable automation frameworks in Python/C++ and streamline DFT workflows using Tcl/Perl/Shell
  • Build APIs and pipelines for Large-scale data ingestion (ATE logs, STIL/WGL patterns) and data processing and visualization dashboards

Qualifications

BE/ME Computer Science, Electronics Engineering or related professions with at least 5-8 years working experience in software development
• Strong expertise in Scan architectures, compression techniques, fault simulation and coverage metrics
• Strong programming expertise in C,C++ or Python and experience in data structures, algorithms, and scalable system design in Linux OS
• Hands-on experience in ML frameworks (PyTorch, TensorFlow) and
data handling (Pandas, NumPy)
• Knowledge of classification, clustering, anomaly detection and feature engineering for semiconductor/test datasets
• Strong attention to details, verbal communication and written skill sets, and ability to work with a highly diverse team-structured environment with positive attitude is mandatory
• Ability to work in a fast paced, project oriented, team environment and escalate any critical issues to the senior management.
Desired
• Experience in electronic measurements/design, and ATE testing, preferably in the digital and High-Speed application domain
• Contributions to test optimization/yield improvement frameworks
• Exposure to GenAI/Copilot-style assistants for debugging or automation
• Experience working with large silicon datasets (production scale)