As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won theGSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out ourwebsiteandGlassdoorpages.
Responsibilities:
Specify, design and implement new arithmetic operators for arithmetic RISC-V instructions, including floating-point, vector, crypto and integer operations.
Optimize timing, area and power usage, or reduce latencies of existing operators
Unit and formal testing for optimizations, writing new tests for new designs
Work with the physical implementation team to optimize physical design to frequency, area, and power targets.
Create documentation to a high standard and collaborate across teams and disciplines.
Requirements
Masters or higher degree in electronic engineering or computer science with a strong mathematical background OR a degree in a related field with a strong background in code development
2+ years of RTL design or related design experience.
Academic or professional experience with arithmetic RTL design or CPU RTL design in Chisel, Verilog, System Verilog or VHDL.
Knowledge of at least one object-oriented or functional programming language and willingness to adopt Chisel hardware generator design
Attention to detail and a focus on high-quality code and documentation.
Ability to work well with others and share the belief that engineering is teamwork.
This is a hybrid working position with 1 office day per week expected; more office days are possible if the successful candidate so prefers
Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in:
United Kingdom
Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
The heart of SiFive is RISC-V! SiFive creates the building blocks of RISC-V-based IP that are the inevitable innovative reimagining of every computing platform.
