Job Description

About Central Engineering Group — Networking Architecture

The CEG Networking Architecture Group defines next-generation networking silicon and platform architecture for hyperscale data centers, cloud infrastructure, and AI workloads. The team focuses on IPU/DPU platforms, advanced packet processing, programmable networking, and the data-movement technologies that enable modern distributed computing systems to scale efficiently.

Position Overview

This role is for a senior AI systems architect who can translate the communication, memory, and orchestration bottlenecks of large-scale AI into networking architecture, IP, and platform direction. The successful candidate will work across research, architecture, silicon, software, and product teams to shape the next generation of distributed AI infrastructure.

As a Senior AI Architect/Researcher, you will help define how AI systems communicate and move data at scale across xPUs, DPUs, IPUs, NICs, memory, and heterogeneous storage. In this pathfinding and research role, you will advance new architectural approaches and translate research insights into network architecture and software capabilities that can influence N+1 to N+3 product roadmap.

The ideal candidate thinks in systems rather than components, understands the memory wall and scale-out serving bottlenecks, and can reason across interconnect, memory hierarchy, software runtime, and compute to unlock the next order of magnitude in AI efficiency. You will help set technical direction and influence silicon and software roadmaps. The candidate is expected to maintain substantial knowledge of state-of-the-art principles and theories, contribute regularly to scientific literature and the research community-at-large, and may participate in the development of Intellectual Property.

Key Responsibilities

Turn Workload Analysis into New IP

• Analyze real AI serving and training workloads, identify communication and memory bottlenecks, and translate those findings into new IP, offload engines, platform features, and architecture requirements
• Drive hardware-software co-design across compute, DPU/IPU, NIC, SoC fabric, and AI serving runtimes, ensuring that networking and data-movement capabilities are reflected in modern inference and training frameworks such as vLLM, SGLang, and others

Architect AI-Scale Networking and Interconnect

• Define the architectural direction for how AI systems and infrastructure move data at scale across xPU-to-xPU, xPU-to-storage, and cross-node paths spanning IPU/DPU platforms, NICs, and heterogeneous storage
• Shape next-generation packet processing, RDMA-class transport, and programmable networking IP that forms the backbone of hyperscale AI inference and training

Attack the Memory Wall and System-Level Bottlenecks

• Investigate the fundamental data-movement bottlenecks in large-scale AI and Agentic inference and training, including KV-cache transfer, disaggregated prefill/decode, model and tensor parallelism, and communication collectives, and translate them into concrete architectural requirements
• Reason across the full memory hierarchy and interconnect to minimize copies, latency, and bandwidth overhead, balancing latency-sensitive control paths against bandwidth-intensive data-paths

Set Roadmap and Lead Across Teams

• Shape multi-generation compute, memory, and interconnect roadmaps across IPU/DPU product lines by defining scaling strategies, migration paths, and architecture requirements that connect research insights to product execution
• Align architecture across networking, SoC fabric, firmware/OS/drivers, and performance modeling teams

What We're Looking For

To be successful in this role, you should demonstrate the following professional traits:

• Architectural vision — defines long-term strategy across AI systems, networking, memory, and software domains
• Influence without authority — drives alignment across multiple teams and disciplines
• Systems thinking — understands interactions across compute, memory, network, and software
• Decision-making under ambiguity — makes sound tradeoffs with incomplete data
• Collaboration — builds strong cross-functional relationships
• Customer-oriented mindset — translates workload needs into architectural innovations
• Ownership and accountability — drives initiatives end-to-end
• Continuous learning — stays current with evolving AI systems, inference runtimes, interconnects, memory technologies, and cloud infrastructure trends

A strong candidate will have enough depth to reason from first principles, enough practical experience to understand implementation constraints, and enough leadership range to align research, architecture, software, and silicon teams around a coherent direction.

Qualifications:

Minimum Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field with 5+ years of relevant experience; or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field with 2+ years of relevant experience

The experience must include:

• Experience with modern AI training and/or inference systems, including model architecture internals, hardware algorithm code design, serving runtimes, and the memory and data-movement bottlenecks that govern large-scale performance
• Hands-on experience with modern inference and training serving stacks such as vLLM, SGLang, and others, with practical understanding of disaggregated prefill/decode, model parallelism, tensor parallelism, and the communication patterns they create
• Experience in computer architecture and system-level design, with a focus on networking, interconnect, or memory subsystems
• Proficiency in C/C++ and/or Python

Preferred Qualifications

• Experience with memory hierarchy and system bottleneck analysis, including caches, memory controllers, bandwidth/latency tradeoffs, and the memory wall as it applies to data-intensive workloads
• High-performance networking and data-movement technologies such as RDMA/RoCE, InfiniBand, or equivalent transport and interconnect
• Experience with IPU/DPU/SmartNIC or accelerator-centric SoCs, particularly in cloud and hyperscale environments
• Familiarity with PCIe, CXL, and memory semantics for high-performance IO
• Experience defining architecture from concept through silicon, platform software, or shipping product, including translating workload analysis into architecture requirements and new IP
• Track record of cross-team technical leadership and influencing architecture and roadmap at a senior level

Intel invests in our people and offers a complete and competitive package of benefits for employees and their families through every stage of life.

Job Type

Experienced Hire

Shift

Shift 1 (United States of America)

Primary Location

US, Oregon, Hillsboro

Additional Locations

US, California, Folsom, US, California, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $195,200.00-275,580.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.