Job Description

Locations: San Jose, California

Categories: Engineering

Req ID: 85806

Hiring Target Min: USD $141,760.00/Yr.

Hiring Target Max: USD $212,640.00/Yr.

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE:

Join our leading-edge RTL Design Methodology team as a Hardware Development Engineer, where you will contribute to the development of next-generation FPGA products. In this role, you will help define and improve the methodologies and tools that enable high-quality RTL design across our engineering organization.

Working closely with RTL designers and verification engineers, you will support the deployment and improvement of front-end design and static verification flows that ensure robust, high-quality silicon. This is an excellent opportunity to build deep expertise in advanced FPGA development while contributing to methodologies used across the company.

THE PERSON:

You are an early-career RTL or design methodology engineer who enjoys solving complex technical problems and learning new tools and flows. You thrive in a fast-paced engineering environment and are motivated by the opportunity to improve design productivity and quality.

You are comfortable working on a small, highly capable team where initiative and ownership are valued, and you enjoy collaborating with design and verification teams to continuously improve engineering processes.

KEY RESPONSIBILITITES:

• We will guide you as you ramp up on our RTL design and static verification tools and methodology ecosystem.
• Collaborate with the design team to drive continuous improvements in front-end design methodologies, ensuring top-quality RTL across areas such as Lint, CDC, formal equivalence, and low-power verification.
• Leverage corporate AI systems to increase productivity and streamline workflows.

PREFERRED EXPERIENCE:

• Experience in logic design and static verification (SystemVerilog, Verilog, or VHDL).
• Strong background in RTL/logic design.
• Programming skills in Perl, Python, and TCL.

ACADEMIC CREDENTIALS:

• Bachelor's degree in Electrical or Computer Engineering; Master's or PhD degree preferred.

LOCATION: San Jose, CA

This role is not eligible for visa sponsorship.

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.