Lead the end-to-end design of complex ASIC subsystems, including specification, architectural exploration, IP evaluation/selection, integration, verification planning, and post-silicon validation.
Drive architecture and micro-architecture trade-offs across features, performance, power, and area. Define clean interfaces and deliver production-quality RTL (Verilog/SystemVerilog).
Implement and verify designs at both block and subsystem levels (using UVM/formal as needed); set coverage goals and drive sign-off.
Define constraints and close timing: author SDC, run STA (setup/hold, OCV/derates), perform CDC/RDC analysis, and collaborate with PD on floorplanning and CTS.
Perform simulation and emulation (FPGA/emulator), debug waveforms/logs, and correlate pre- and post-silicon behavior.
Define and implement DFT/DFD strategies (scan, MBIST/LBIST, boundary scan/JTAG); support ATPG and test bring-up.
Maintain high code quality with lint, CDC/RDC, LEC, and synthesis-friendly design practices; manage ECOs where necessary.
Build automation flows: develop Tcl/PrimeTime scripts for skew analysis, clocking, and core-to-IO interfaces (PCIe, 400GE, UCIe).
Write clear specifications, micro-architecture docs, and user guides for downstream engineering teams.
You will work closely with:
Silicon architects shaping next-generation AI compute platforms.
Verification engineers ensuring design robustness.
Firmware and Linux driver engineers building the software stack.
Security teams protecting customer assets.
Compiler and ML framework teams optimizing workload mapping.
System validation engineers ensuring enterprise-grade reliability.
7+ years of experience in RTL design and ASIC development.
Strong proficiency in Verilog/SystemVerilog
Hands-on experience across the entire chip development lifecycle
Proven expertise in complex IP integration (e.g., multi-core CPUs, NoCs, GPUs/NPUs, or high-speed interfaces like PCIe, 100/400G Ethernet, UCIe).
Experience writing specifications and converting them into robust designs.
Deep understanding of multiple clock domains and asynchronous interfaces
Familiarity with AMBA bus protocols (AXI, AHB, APB).
Experience in power and clock management design
Proficiency with formal equivalency checking (RTL ↔ Netlist).
Experience with DFT implementation
Understanding of AI accelerator architectures (systolic arrays, dataflow, tiling).
Experience with memory bandwidth optimization and HBM/GDDR integration
Exposure to first-silicon bring-up with real AI workloads.
Strong scripting skills (Tcl, Python) for automation and timing/debug flows.
Deep RTL Mastery 7+ years of building and shipping production-quality RTL (Verilog/SystemVerilog).
Subsystem Ownership Has taken IP or subsystems from spec → RTL → timing closure → silicon validation
IP Integration Experience Worked with complex IPs like CPUs, NoCs, GPUs/NPUs, or high-speed I/O (PCIe, 400GE, UCIe).
Timing & Debugging Skills Knows how to close timing, write constraints (SDC), run STA, and debug across FPGA/emulation and silicon.
Breadth Across the Flow Comfortable with DFT/DFD, power/clock domains, CDC/RDC, and automation scripting.
AI Accelerator Insight (bonus): Exposure to systolic arrays, dataflow architectures, and high-bandwidth memory subsystems (HBM/GDDR)
MBR Partners is a globally orientated recruitment business focused on talent acquisition across Technology areas (Telecoms, Security, Finance, Mobility, Enterprise Software, ITO & BPO Outsourcing and Utilities).
Established in 2001, MBR has a proven track record for delivering high calibre talent solutions. We pride ourselves on supporting our clients globally across C-level, leadership, sales, presales, delivery, marketing and technical requirements.
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