Job Description

Company:

Qualcomm Israel Ltd.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.

Qualcomm is expanding its team in connectivity networking products engineering Team. We are looking for experienced SoC RTL design engineers to contribute to our next generation connectivity networking products. This is an incredible opportunity to be part of the AI revolution and contribute to the complete semiconductor development cycle, from concept to product.

The ideal candidate will have a strong and extensive background in RTL design across multiple projects. As an experienced RTL Design Engineer, you will work in SoC design and SOC-Subsystem design. You will be responsible for microarchitecture/RTL coding of the SOC/subsystems and create microarchitecture documents. You will work with verification teams on achieving the code & functional coverage. You will work with Physical design team to meet area, power and performance goals. You will support physical design teams, verification teams, software teams and FPGA teams to ensure high quality SoC and ensure successful tapeout.

Why Join Us?

• Work on cutting-edge SoC designs in advanced process nodes.
• Products purpose-built for AI datacenter scale out and scale up connectivity
• Work in a high-impact, fast-paced environment.
• Competitive compensation and career growth opportunities.
• Work alongside some of the best minds in the semiconductor industry.

What You'll Do

• Micro architect and RTL Design of SoC SubSystem/IP blocks
• Will be responsible for RTL quality checks - Lint/CDC/LEC
• Create appropriate documentation for hardware blocks
• Responsible for analyse / debug / fixing issues reported by verification team
• Will develop the synthesis constraints for the blocks / subsystem
• Work with SOC Architect/Leads to integrate the design, review/sign-off verification plan, DFT and PD implementation

What You'll Need

• Strong background with multi-year and multi-project experience in RTL SoC Design (Verilog/VHDL), and ASIC/FPGA debug methodologies
• Experience in SerDes PHY, DSP, and Analog mixed signal is desirable
• Knowledge in Ethernet and PCIe standards is desirable
• Test Plans & Verification: Proficient in reviewing high-level test plans and coverage metrics.
• Synthesis & Formal Verification: Expertise in Design Compiler Synthesis and formal verification using LEC.
• Timing Closure: Comprehensive understanding of timing closure.
• Communication & Leadership: Team player with strong communication skills to ensure effective program execution.

It Would Be Amazing If You Had

• Architecture: Ability to develop architecture and micro-architecture based on specifications.
• Bus Protocols & Peripherals: Knowledge of bus protocols such as AHB, AXI, and peripherals like PCIe, USB, Ethernet, etc.

*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

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