Developing precise test cases for FILL/DRC/LVS rules based on foundry decks with good quality by Virtuoso
Working closely with PE and R&D for new features/enhancements of Pegasus
DRC/FILL/LVS/PERC including deck coding/QC pattern generation
Assuring the quality of physical validation tool Pegasus by analyzing existing test suites
Validating code changes and integrating customer cases as part of regression test suite
Requirements
Good at Virtuoso for simple pattern creation (familiar with SKILL is a plus)
With experience in developing and supporting physical verification activities in FILL/DRC/LVS area
Solid knowledge of foundry layout rules and device identification concepts
Working experience with UNIX and knowledge for shell/tcl scripting languages (familiar with Perl and/or python is a plus)
Should be able to work independently and have adequate personality & communication skills to cooperate with cross functional groups
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.
