1. Assist in Cadence Genus/Innovus/Tempus (Back-End & signoff Design Tool) development and validation;
2. Develop testsuites to ensure the good STA quality, ensure the correctness of timing analysis in each stage of the digital implantation flow
3. Assist in Cadence Innovus RC extraction verification for advanced nodes
Additional Job Description
1. The candidate should be familiar with Linux system, and proficient scripting skills with TCL/PERL/Shell/Python;
2. The candidate should have MS degree, or bachelor degree with 3+ years of digital design experience;
3. The candidate should be familiar with digital circuit design implementation flow, STA/Extraction knowledge is a preference;
4. Good team player with strong written and verbal communication skills, and with good patience & responsibility.
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.
