Job Description

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more atwww.silabs.com

PrincipalStatic Timing Analysis Engineer
Austin, TX

This positioninvolves the development of timing constraints and timing closure signoff of low power Wireless SoCs and IP systemsThese SoC devices are multi-core, multi-threaded processor subsystems with multi-level cache, capable of supporting multiple wireless protocols and application functionality, such as sensor hub, AI /MLand are specified to exceed best-in-classpower targetsThese SoCs deploy a complex, deeply gated clock network with many asynchronous clock sources

Responsibilities

• Develop timing constraints at both the IP and SoC level in collaboration with the designers

• Improve or evolve existing static timinganalysisflows and methodologies

• Developrequired timing signoff criteria, such as aging, on chip variation,andsignal integrity

• Analyze timing reports using scripting techniques to develop insights and drive rapid timing closure

• Collaborate with a global design team to resolve complex static timing issues

• Collaborate with a multi-functional team to drive timing closure for mixed-signal IP integration
  

Skills You Will Need

Minimum Qualifications

• 15+ yearsin Industry

• BachelororMaster’s degree in Electrical or Computer Engineering

• In depth knowledge of the timing closure flow andmethodology

• Experience intiming constraint development, both functional and test modes (such as scan)

• Hands-on experiencewith static timing tools, such as Tempus or Primetime

• In depth knowledge of scripting languages like Perl, Python,Tcl, shell

• Knowledge oftiming closuremodes and corners

• Knowledge of low power designmethodology(static/dynamic clock gating, power gating, dynamicvoltageand frequency scaling)

• Knowledge oftiming model generation of mixed signal IP

• Knowledge of design flows including Lint, CDC, Synthesis,Logic Equivalence, DFT, Place and Route

• Knowledge of Verilog and System Verilog
  

• Experience with artificial intelligence (AI) powered tools and technologies used to enhance productivity, analysis, and decision-making
  

Benefits & Perks

You can look forward to the following benefits:

• Great medical (Choice of PPO or Consumer Driven Health Plan with HSA), dental and vision plans

• Highly competitive salary

• 401k plan with match and Roth planoption

• Equity rewards (RSUs)

• Life/AD&D and disability coverage

• Flexible spending accounts

• Adoptionassistance

• Back-Up childcare

• Additionalbenefit options (Commuter benefits, Legal benefits, Pet insurance)

• Flexible PTO schedule

• 3 paid volunteer days per year

• Charitable contribution match

• Tuition reimbursement

• Free downtown parking

• Onsite gym

• Monthly wellness offerings

• Free snacks

• Monthly company updates with our CEO
  

#LI-KB1

#LI-Hybrid

The annualized base pay range for this role is expected to be between $160,650 - $298,350 USD. Actual base pay could vary based on factors including but not limited to experience, geographic location where work will be performed and applicant’s skill set. The base pay is just one component of the total compensation package for employees. Other rewards may include an annual cash bonus, equity package and a comprehensive benefits package.

Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.