Job Description

Locations: San Jose, California

Categories: Engineering

Req ID: 97768

Hiring Target Min: USD $209,600.00/Yr.

Hiring Target Max: USD $314,400.00/Yr.

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

Role Summary

Advanced packaging is at the center of everything happening in semiconductors right now — AI accelerators, next-generation FPGAs, embedded SoCs, and custom ASICs are all pushing the limits of what packaging technology can deliver. AECG Packaging is where that work gets done.

We are looking for a Principal Packaging Integration Engineer who can do two things exceptionally well: drive technically sound packaging architecture decisions and be the trusted engineering partner our customers rely on to bring those decisions to life.

This is not a support role. You will own your programs — technically and commercially — from architecture through qualification, pulling together design, process, quality, test, and supply chain into decisions that are smart, manufacturable, and on schedule.

If you are a seasoned packaging engineer who has outgrown pure technical execution and wants a role where your judgment, relationships, and technical depth all matter equally — this was written for you.

Key Responsibilities

• Drive packaging architecture decisions and IC-PKG-PCB co-design for FPGA, embedded SoC, and custom ASIC programs spanning 2.5D/3D, OPC, and MOP technologies.
• Lead DFM and DFMEA reviews and packaging supply qualification, partnering with OSAT/substrate suppliers on manufacturable, reliable, application-ready solutions.
• Serve as the primary customer-facing contact for assigned programs — representing the packaging organization and translating customer requirements into internal technical direction.
• Organize and lead cross-functional task forces across silicon design, packaging, SI/PI, thermal-mechanical, quality and reliability test, and supply chain to resolve issues, align decisions, and keep programs on schedule.
• Proactively fill gaps between functional groups and track commitments to genuine closure.
• Build durable, trusted relationships with customers and internal partners through responsive, patient, detail-oriented follow-through.

Qualifications

• Expert-level experience in semiconductor packaging technology integration, with working knowledge of 2.5D/3D integration, OPC, MOP, and IC-PKG-PCB co-design and co-development.
• Strong experience with DFM/DFMEA/PFMEA and packaging supply qualification (OSAT/substrate/materials partners).
• Demonstrated experience engaging customers directly and coordinating cross-functional task forces to closure.
• Fluent, confident communicator with both engineering teams and customers; detail-oriented, patient, and customer-driven.
• Willing to step out to fill gaps between functional groups and drive issues to closure.
• Bachelor's or Master's degree in Electrical, Materials, Mechanical, or Semiconductor Engineering, or a related field.

Preferred Skills

• Strong knowledge of SoC architecture and critical IP blocks (SerDes, PHYs, memory controllers, I/O subsystems) and how they drive packaging and interconnect requirements.
• Familiarity with IC-package-PCB co-design and analysis tools (e.g., Cadence, Synopsys, Ansys, or equivalent EDA platforms).
• Familiarity with UCIe (Universal Chiplet Interconnect Express) and other die-to-die/chiplet interconnect standards.
• Experience with signal integrity and power integrity (SI/PI) analysis across the package and board interconnect.
• Understanding of high-speed I/O interface design considerations at the package level.
• Familiarity with DDR/memory interface routing, timing, and packaging constraints.
• Experience with power plane and PDN (power delivery network) optimization across silicon, package, and board.
• Ability to evaluate design considerations and trade-offs (performance, cost, manufacturability, reliability, schedule) and communicate them clearly to both engineering and customer stakeholders.

This role is not eligible for visa sponsorship.

#LI-BW2

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.