We are seeking a highly motivated Principal Engineer Design to lead the physical implementation and timing closure of advanced low-power SoCs targeting the IoT and MCU markets. This role offers the opportunity to drive end-to-end physical design execution, optimize power, performance, and area (PPA), and influence methodology improvements that enable successful silicon delivery.

The ideal candidate will possess deep expertise in physical design, timing convergence, low-power implementation methodologies, and signoff processes while demonstrating strong technical leadership and cross-functional collaboration skills.

• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Computer Engineering, or a related discipline.
• 8+ years of hands-on experience in Physical Design and Timing Closure for complex SoC products.
• Proven success in driving chip implementation from floor planning through tape out and silicon delivery.
• Strong understanding of advanced semiconductor process technologies and associated physical design challenges.
• Experience delivering low-power SoCs for IoT, MCU, consumer, mobile, automotive, or related applications.

Technical Skills & Expertise

• Deep expertise in hierarchical SoC physical design, implementation, and timing convergence.
• Strong proficiency with industry-standard Physical Design, Signoff, and EDA automation tools.
• Hands-on experience in:
  • Floor planning and physical partitioning
  • Power planning and power grid design
  • Place and Route (P&R)
  • Clock Tree Synthesis (CTS)
  • Static Timing Analysis (STA)
  • Multi-mode, multi-corner (MMMC) timing closure
  • Physical verification and signoff
  • EM/IR and power integrity analysis
• In-depth knowledge of low-power design methodologies and implementation techniques.
• Strong understanding of process technology trade-offs affecting Power, Performance, and Area (PPA).
• Ability to analyze and solve complex implementation challenges through data-driven decision-making and technical collaboration.

Leadership & Collaboration

• Drive technical decisions and take ownership of implementation quality, schedule, and deliverables.
• Collaborate effectively with cross-functional teams across Architecture, RTL, Verification, DFT, Packaging, and Foundry organizations.
• Lead technical discussions, design reviews, and implementation strategy planning.
• Mentor and develop junior engineers while fostering a culture of technical excellence.
• Promote knowledge sharing, best practices, and continuous learning across teams.
• Champion innovation in methodologies, design flows, automation, and tool usage.
• Demonstrate strong communication, stakeholder management, and problem-solving capabilities.