We are looking for a Design Engineer (7-12 years) to join our PCIe Design Team, working on next‑generation high‑speed interface IPs.
🔹 Key Responsibilities & Skills
Must Have : Hands‑on experience in PCIe design and micro‑architecture
Strong proficiency with design tools and a solid understanding of PPA (Performance, Power, Area) optimization techniques
Must Have : Good knowledge of scripting and applying AI-assisted design tools in the development flow
Strong debug skills and ability to collaborate closely with DV teams to resolve design issues
Highly Desired Skill : knowledge on Integrity and Data Encryption (IDE) : AES Encryption/Decryption algorithm along with GCM protocol.
Desired Skill : Automotive/FuSa experience
🎓 Qualifications
B.Tech / M.Tech in Electronics, Electrical, or Computer Science
If you’re passionate about high-speed interfaces and enjoy working on complex, performance‑critical designs, we’d love to connect.
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.
