Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 3 years of experience in architecture, hardware, digital design, and software co-design.
  
• 2 years of experience in Verilog/SystemVerilog.
  
• Experience in computer architecture and digital design or IP integration (e.g., Peripheral Component Interconnect Express (PCIe), Double Data Rate (DDR) memory).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• 4 years of experience working on Field Programmable Gate Array (FPGA) platforms or Emulation platforms with IPs (e.g., Peripheral Component Interconnect Express (PCIe), Double Data Rate (DDR) memory, Gigabit Ethernet, Flash).
• Experience in developing architectures for machine learning accelerators.
• Experience in writing or debugging Verilog/Register-Transfer Level (RTL) code for ASIC/FPGA designs, waveform debug skills with knowledge of chip design flows.

About the job

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Enable bring-up of chip features through firmware and driver stack. Integrate and validate hardware and software designs in pre-silicon.
• Architect and design Application-Specific Integrated Circuit (ASIC) models for Emulation/Field Programmable Gate Array (FPGA) Prototypes. Design Register-Transfer Level (RTL) transformations to optimize mapping to Emulation/FPGA platforms and design solutions to improve IP modeling.
• Design solutions to improve hardware modeling accuracy and scale to various system configurations and enable serving of ASIC models for software and validation teams.
• Bring up chip features on software reference models and hardware prototypes (e.g., Emulation/FPGA) and drive debug discussions with design/design validation/physical design/software/architecture teams and help root-cause failures.
• Develop the integration plan with software and system partners, coordinate hardware and software delivery and benchmark performance.