Job Description

Job Summary

This role is accountable for guiding technology decisions and solution delivery in complex projects centered on STD-Cell characterization. The position requires advanced proficiency in implementing, optimizing, and overseeing technical processes, directly driving delivery outcomes and technical excellence within the team and across assigned projects. They will ensure high standards of quality, compliance, and innovation in all aspects of STD-Cell characterization work.

Key Responsibilities

1. Provide advanced proficiency in STD-Cell characterization using industry-standard EDA tools (such as Cadence, Synopsys, or Mentor Graphics), guiding team members in accurate cell modeling and validation.
2. Oversee and refine quality assurance processes for STD-Cell libraries, including performance optimization, timing analysis, and signal integrity verification with tools like SPICE simulators and Liberty format checks.
3. Establish and implement best practices for cell characterization workflow, ensuring compliance with process guidelines and technical standards.
4. Participate in technical feasibility studies and risk assessments for new STD-Cell projects, evaluating alternative methodologies and supporting architectural best practices.
5. Collaborate with internal stakeholders to define project scope and deliverables, preparing detailed status reports and contributing to escalation management and resolution.

Skill Requirements

1. Advanced proficiency in STD-Cell characterization, including hands-on use of EDA tools (Cadence, Synopsys, Mentor Graphics).
2. Solid expertise in cell modeling, timing analysis, and performance optimization techniques.
3. Strong understanding of quality assurance processes and compliance standards in semiconductor library development.
4. Experience in technical feasibility analysis and risk evaluation for STD-Cell projects.
5. Effective communication skills for collaborating within the team and with project stakeholders.

Other Requirements

1. Optional but valuable: Certification in VLSI Design or related EDA tool certifications (Cadence Certified, Synopsys Certified).