Job Description

This role is for one of the Weekday's clients

Salary range: Rs 1000000 - Rs 1500000 (ie INR 10-15 LPA)

Min Experience: 4+ years

Location: Bengaluru

JobType: full-time

We are looking for a Physical Verification (PV) Engineer to join our VLSI Physical Design team. In this role, you will be responsible for executing physical verification flows, identifying and resolving layout issues, and ensuring designs meet signoff quality requirements. The ideal candidate should have strong hands-on experience with industry-standard physical verification tools and a solid understanding of physical design methodologies.

You will collaborate closely with Physical Design, Layout, and Design teams to achieve clean signoff and deliver high-quality silicon.

Requirements

Key Responsibilities

• Execute block-level Physical Verification (PV) flows for complex VLSI designs.
• Perform physical verification checks including DRC, LVS, ERC, and other signoff validations using industry-standard tools.
• Analyze, debug, and resolve physical verification violations to achieve signoff-quality layouts.
• Work closely with Physical Design and Layout teams to identify root causes and implement layout fixes.
• Support signoff activities by ensuring compliance with foundry rules and design methodologies.
• Develop and maintain automation scripts to improve verification efficiency and productivity.
• Perform detailed debugging and verification of layout-related issues.
• Collaborate with cross-functional teams to ensure timely project execution and successful tape-out.
• Maintain verification documentation and support continuous improvement of PV methodologies.

Required Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field.
• Strong experience in Physical Verification (PV) for advanced semiconductor designs.
• Hands-on expertise with Calibre, Fusion Compiler (FC), and Cadence Innovus
• Good understanding of Physical Verification methodologies and signoff flows.
• Experience debugging layout violations and resolving DRC/LVS/ERC issues.
• Strong scripting skills using TCL, Perl, or Shell
• Excellent debugging, analytical, and problem-solving skills.
• Strong communication and collaboration abilities.

Preferred Qualifications

• Experience with advanced process nodes.
• Familiarity with physical design flow and timing closure concepts.
• Knowledge of layout optimization techniques and tape-out processes.
• Exposure to automation frameworks for physical verification.

Must-Have Skills

• Physical Verification (PV)
• Calibre
• Fusion Compiler (FC)
• Cadence Innovus
• DRC
• LVS
• ERC
• Layout Verification
• TCL / Perl / Shell Scripting

Good-to-Have Skills

• Physical Design Flow
• Timing Closure
• Advanced Node Experience
• Automation Frameworks
• Tape-out Support
• Layout Optimization