Job Description

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

QCT’s DSP Team is actively seeking talented Physical Design Engineers to join our DSP PD team. As a Physical Design Engineer, you will innovate, develop, and implement DSP cores using state-of-the-art tools and technologies. This role requires strong expertise in physical design flow, tapeout readiness, and Power, Performance, and Area (PPA) optimization for advanced technology nodes. Backfill.

Key Responsibilities

• Own and execute complete Physical Design flow from netlist to GDSII, including:
• Floorplanning, power planning, IR-drop analysis
• Placement, MMMC clock tree synthesis, routing
• Timing optimization and closure across multiple modes and corners
• Perform PPA analysis and optimization to meet aggressive power, performance, and area targets.
• Develop and enable low-power implementation methods and customized P&R strategies for area reduction and performance improvement.
• Debug timing violations, implement timing fixes, and roll in functional ECOs.
• Conduct RC extraction, signal integrity, crosstalk noise/delay analysis, and formal verification.
• Manage tapeout activities, ensuring sign-off for DRC, LVS, timing, power integrity, and reliability.
• Collaborate with RTL, architecture, and verification teams to influence design decisions for optimal PPA.
• Contribute to flow enhancements and automation using scripting (Perl/TCL, Python, Linux shell).

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• 3+ years of industry experience in Physical Design for ASIC/SoC.
• Proven tapeout experience with successful delivery of complex cores.
• Hands-on expertise with:
  • Place & Route tools: Cadence Innovus and/or Synopsys ICC2/Fusion Compiler
  • Timing closure: Synopsys PrimeTime
  • Physical verification: DRC/LVS sign-off flows
• Strong understanding of DFT, multi-mode/multi-corner designs, and ECO flows.
• Proficiency in scripting languages (Perl, TCL, Python) and Linux/Unix environments.

Preferred Skills

• Experience with latest advanced technology nodes.
• Knowledge of power integrity analysis (IR-drop, EM) and low-power design techniques.
• Familiarity with formal verification , understanding of DFM and post-silicon validation .
• Ability to work in a fast-paced environment and communicate effectively with cross-functional teams.

Why Join Us?

• Work on cutting-edge DSP cores for next-generation products.
• Opportunity to lead tapeout and PPA optimization for high-performance, low-power designs.
• Collaborative team environment with strong focus on innovation and technical excellence.

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Pay range and Other Compensation & Benefits

$115,600.00 - $173,400.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link

If you would like more information about this role, please contact Qualcomm Careers