Job Description

The Role and Impact:
As a Physical Design Engineer, you will be at the forefront of crafting high-quality custom IP and SoC designs, translating RTL into manufacturing-ready databases. Your day-to-day activities will involve implementing key stages of the physical design flow, including synthesis, place and route, clock tree synthesis, and static timing analysis. By optimizing designs for power, frequency, and area, you will directly contribute to delivering industry-leading solutions that drive Intel's technological leadership.

Business group:
The Physical Design Engineering team operates within Intel's cutting-edge design ecosystem, focusing on the development of high-performance and reliable silicon solutions. This group enables the creation of innovative technologies by supporting architectural and design excellence, ensuring Intel's continued success in delivering industry-leading products to customers worldwide.

Key Responsibilities:

• Perform physical design implementation of custom IP and SoC designs from RTL to GDSII.
• Execute all aspects of the physical design flow, including synthesis, place and route, floor planning, clock tree synthesis, and static timing analysis.
• Conduct verification and signoff processes, including formal equivalence checks, reliability verifications, and layout verification.
• Analyze results from power integrity, noise analysis, and timing closure to ensure design convergence.
• Optimize designs to improve critical product parameters such as power, frequency, and area.
• Collaborate on the development and enhancement of physical design methodologies and flow automation.

Qualifications:

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with 0-1 years of hands-on experience in physical design gained through internships, academic projects, coursework, or hands-on training.

Or

• Master's degree in Electrical Engineering, Computer Engineering, or a related field with no prior professional experience.
• Demonstrated proficiency in physical design methodologies, flows, and EDA tools (e.g., synthesis, place and route, timing analysis).

Preferred Qualifications:

• Knowledge of VLSI design methodologies, including clock tree synthesis, timing closure, and coverage analysis.
• Familiarity with scripting languages such as Perl or TCL and proficiency in hardware description languages like Verilog or VHDL.
• Strong problem-solving skills with a detail-oriented approach to design challenges.

Join us to shape the future of technology and collaborate with industry-leading professionals on groundbreaking solutions. We look forward to welcoming your expertise to our team.

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.