Job Description

The Role and Impact
Join Intel's HIPD - SAM group as a Physical Design Engineer, where you will play a pivotal role in shaping high-speed mixed-signal IP designs that power Intel's innovations across server, client, and graphics microprocessors. In this dynamic position, you will collaborate with architects, logic designers, and analog engineers to implement complex features from RTL to GDS. Your contributions will directly impact Intel's leadership in advanced semiconductor technologies, driving next-generation computing platforms and delivering groundbreaking performance improvements.

Key Responsibilities
- Create a design database that is ready for manufacturing and has completed sign-off flows.
- Conduct power supply and power grid planning and analysis to ensure robust power delivery networks.
- Perform logic synthesis, place-and-route, and clock tree synthesis using industry-standard tools like Synopsys and Cadence.
- Execute verification processes, including formal equivalence verification (FEV), static timing analysis (STA), and physical verification (LVS, DRC, and antenna checks).
- Optimize designs to enhance parameters such as power, frequency, and area while ensuring high reliability.
- Conduct power integrity analysis (IR/RV) and implement techniques for power reduction.
- Debug and resolve integration issues at the SoC level, collaborating across teams to ensure seamless operation.
- Participate in design reviews and manage sign-off flows for manufacturing readiness.
- Develop and improve physical design methodologies and flow automation processes.

Qualifications:

Minimum Qualifications
- Bachelor's degree in Electrical Engineering or Electronics Engineering with 0-1+ years of relevant experience, or a Master's degree in Microelectronics/VLSI with 0 years of relevant experience per business needs.
- Proficiency in industry-standard EDA tools such as Synopsys Design Compiler, Cadence Innovus, and Prime Time for physical design.
- Knowledge of physical design flows and methodologies, including RTL-to-GDS implementation.
- Familiarity with static timing analysis, layout verification processes, and reliability verification techniques.

Preferred Qualifications
- Foundational understanding of complementary MOS (CMOS) circuit design principles.
- Knowledge of digital logic optimization and trade-offs in circuit design related to power, performance, and area.
- Experience with low-power implementation techniques and multiple power domain analysis.
- Coursework or hands-on practice with Very Large-Scale Integration (VLSI) design and physical design flows.
- Strong analytical skills, effective communication, and a continuous-learning mindset.

We invite you to bring your expertise to Intel and help us drive innovation, transform industries, and shape the future of computing technology. Apply now to be part of our mission to deliver world-class products and solutions.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.