Job Description

As a Physical Design Engineer, you will play a pivotal role in Intel's journey to delivering world-class custom IP and SoC designs. Embedded in a vibrant and collaborative environment, you will transform RTL into manufacturing-ready design databases, harnessing cutting-edge industry EDA tools and methodologies. Your contributions will directly influence Intel's ability to innovate at leading-edge process nodes, optimizing the design to achieve exceptional power, performance, and area (PPA) metrics. This is a unique opportunity to drive the development of next-generation technologies, leaving a lasting impact on Intel's product portfolio and its position as a global leader in semiconductor design.

Key Responsibilities:

• Execute all stages of the physical design flow, including synthesis, floor planning, placement, routing, clock tree synthesis, and static timing analysis.
• Conduct verification and signoff activities such as formal equivalence verification, layout verification, reliability checks, and power/noise analysis.
• Drive timing closure efforts using industry-standard tools like Primetime, working to meet stringent design and signoff requirements.
• Analyze timing reports, debug issues, execute timing ECOs, and deliver feedback to optimize design methodologies.
• Develop and refine power/clock distribution strategies to ensure robust and efficient designs.
• Collaborate closely with architecture, design, and implementation teams to define constraints, clocking specifications, I/O budgets, and achieve IP budget convergence.
• Enhance design flows and automation processes to accommodate evolving technology and product architecture needs.
• Mentor junior engineers, fostering skill development and technical excellence within the team.

Qualifications:

Minimum Qualifications:

• Bachelor's degree in Electrical or Computer Engineering, or related field, with 2+ years of experience; or a Master's degree with 1+ years of experience; or a PhD with 0 years of experience in the structural/physical design domain.
• Experience with the entire RTL-to-GDS flow, including physical design methodologies, STA, and timing signoff.
• Demonstrated expertise in EDA tools such as Primetime, ICC, or Innovus for physical design and verification tasks.
• Proficiency in scripting languages like Perl, TCL, and automation of design workflows.
• Solid understanding of low-power and advanced design techniques for deep sub-micron process nodes.

Preferred Qualifications:

• Multiple tape-out experiences on advanced technology nodes.
• Expertise in developing SDC constraints, timing budgeting, and ECO implementation.
• Familiarity with hardware description languages such as Verilog or VHDL.
• Proven ability to work collaboratively across diverse teams, with strong analytical and problem-solving skills.

Join us in shaping the future of semiconductor design. Apply today and become an integral part of Intel's mission to push the boundaries of technology and innovation.

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.