Job Description

Minimum qualifications

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
• 8 years of experience in physical design engineering.
• Experience in managing high performance design schema utilizing CPU or GPU.

Preferred qualifications

• Master's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
• Experience with power optimization techniques.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Responsibilities

• Develop all aspects of ASIC RTL2GDS implementation for high Power, Performance, and Area (PPA) designs.
• Manage block and full-chip level physical implementation and Quality of Results (QoR) (power, timing, area).