Job Description

ABOUT THE ROLE

As a Sr Staff / Principal CAD & Design Methodology Engineer, you will be the technical architect of RTL-to-GDSII flows and digital design infrastructure for advanced SoC products. You will define and deploy multi-vendor, multi-foundry design methodology platforms, lead hierarchical SoC implementation strategies, and drive low-power chiplet products. You will own the R2G (RTL-to-GDSII) system architecture spanning Intel, TSMC, Samsung, and GlobalFoundries nodes — enabling scalable, high-quality tapeouts across diverse product classes.

KEY RESPONSIBILITIES

RTL-to-GDSII Flow Architecture & Development

• Architect, develop, and maintain a comprehensive RTL-to-GDSII digital implementation flow supporting multi-level hierarchical SoC designs using both top-down and bottom-up methodologies.
• Define R2G flow architecture that integrates best-in-class EDA tools from Synopsys, Cadence, and Siemens — enabling a vendor-agnostic, extensible platform adaptable to evolving foundry PDKs.
• Design the Reference Design and Validation Platform (RDVP) to enable continuous RTL-to-GDSII flow development, regression, and qualification across technology nodes.
• Define design rules, constraint templates, and implementation guidelines specific to each foundry node — ensuring teams adopt correct methodology from project kickoff through tapeout.
• Collaborate with foundry technology teams at Intel Foundry, TSMC, Samsung, and GlobalFoundries to stay ahead of node-specific methodology requirements and PDK updates.
• Lead methodology and execution for low-power core design targeting aggressive PPA targets in accelerator product lines — covering power intent definition, multi-voltage domain management, and clock gating strategy.
• Define and implement CPF/UPF-based low-power flows — covering level-shifter insertion, isolation cell placement, retention register strategy, and power domain crossings verification.
• Own EM/IR methodology for low-power multi-core designs — defining PDN architecture, power strapping strategies, and EM-clean routing guidelines per foundry requirements.
• Architect hierarchical design planning methodology for large, complex SoC designs — defining partition boundaries, interface timing budgets, pin assignment constraints, and hierarchical timing models (ETMs/ILMs).
• Lead top-level and block-level floorplan development — driving macro placement, power domain definition, IO ring planning, and die size optimization for PPA.
• Define and enforce hierarchical constraints — ensuring block-level implementations are physically and electrically compatible at integration, minimizing top-level ECO iterations.
• Define and own comprehensive clocking methodology covering Clock Mesh, Spine-and-Rib, H-Tree, and hybrid topologies — selecting the optimal strategy per design class, frequency target, and power budget.
• Develop custom clock cell libraries and constraints to support low-skew, low-power clock distributions across large multi-core SoCs.
• Define system architecture to leverage external EDA ecosystem tools and methods — accelerating alignment with vendor solutions and reducing new-node bring-up time.
• Define logic synthesis methodology — specifying SDC constraint authoring guidelines, multi-corner multi-mode (MCMM) synthesis strategies, and design-for-test (DFT) integration points.
• Own static timing analysis (STA) methodology — defining corner selection, OCV/AOCV/POCV derate strategies, timing exception management, and hold/setup
• Drive continuous improvement of CAD infrastructure through automation, ML-assisted optimization, and adoption of emerging EDA capabilities.

MINIMUM QUALIFICATIONS

• 15+ years of experience in ASIC CAD, design methodology, or physical design with a proven record of leading multi-node, multi-foundry platform deployments.
• Demonstrated success deploying R2G platforms across multiple external foundry nodes (TSMC N3/N5/N7, Samsung SF3/SF4, GlobalFoundries GF12/GF22).
• Deep expertise in low-power design methodology — UPF/CPF flows, multi-voltage domain integration, retention strategy, and power domain verification.
• Proven expertise in clocking methodologies: Clock Mesh, Spine-and-Rib, H-Tree, and hybrid clock architectures with custom cell integration.
• Familiarity with chiplet and 2.5D integration methodology — die-to-die interface timing, UCIe/BoW PHY integration, and hierarchical top-level assembly flows.
• Exceptional problem-solving ability and communication skills — comfortable presenting to executive leadership and engaging directly with foundry technology teams.