Job Description

About the Role

In this role you'll be responsible to design the next iteration of SEMRON's 3D in-memory compute chip. You will collaborate with a team of hardware, compiler and ML engineers to optimise all aspects of executing ML workloads based on our capacitive analog in-memory matrix-vector multiplication units.

What you will do:

• Design and specify the structure and internal organisation of core architecture modules, aligned with workload requirements and software deployment processes.
• Partner with the software team to evaluate module performance and efficiency for key workloads, uncover performance constraints, and inform architectural choices.
• Monitor emerging trends and research in AI workloads, hardware architectures, and applications to guide the evolution of next-generation architectures.

What you should bring in:

• BS/MS/PhD in EE, CS, or a related field
• Understanding in computer architecture, digital design, and micro-architecture concepts
• Familiarity with AI/ML algorithms, frameworks, and workloads
• Programming experience in C/C++ and Python

Helpful but not required:

• Hands-On Experience with ML Hardware Exploration Frameworks like Timeloop, ZigZag, etc.
• Hands-On Experience with HDLs such as Verilog or System Verilog