Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience in micro-architecture and design of ASIC blocks.
• Experience in designing/implementing Register-Transfer Level (RTL) for one or more blocks: Central Processing Units (CPUs), Graphics Processing Units (GPUs), caches, Memory Management Units (MMUs), or coherent fabrics.
• Experience in micro-architecture/design performance analysis, tools, and simulators.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture.
• Experience in building build time configurable designs.
• Knowledge in one or more of these areas: coherent interconnects, caches, memory systems.
• Knowledge of Hardware Description Languages (HDL) such as SystemVerilog or Verilog.

About the job

In this role, you will shape the future of our coherent memory systems for consumer SoCs. You will leverage your technical expertise in design and uArch to create the most advanced power- and performance-efficient mobile coherent systems. Your work will have a direct impact on the performance, efficiency, and innovation of our next-generation devices. You will work with hardware designers and validation teams to build and test exceptional hardware architectures. As part of this work, you will participate in the development of technology in the memory system and the filing of associated patents.

Responsibilities

• Explore and evaluate different uArch and design choices for power- and performance-efficient coherent and non-coherent memory systems.
• Author hardware uArch specification for next-generation coherent and non-coherent memory systems.
• Analyze performance and power trade-offs.
• Work with hardware design, verification, emulation, and validation teams to build and test the hardware architecture.