
Gimlet is building the first multi-silicon neocloud designed for fast, efficient AI inference.
We combine large-scale compute infrastructure with an execution platform that partitions AI workloads and maps each stage to the hardware best suited to run it.
We work with foundation labs, hyperscalers, and AI-native companies, giving our team access to technical problems spanning frontier models, production infrastructure, and emerging hardware.
As a Member of Technical Staff, you will characterize and improve the performance of production AI inference across Gimlet's heterogeneous accelerator fleet.
You will work across kernel execution, compiler output, runtime behavior, memory movement, synchronization, scheduling, and multi-device execution. Rather than treating performance as a collection of isolated microbenchmarks, you will connect hardware-level evidence to end-to-end latency, throughput, utilization, and cost.
You will build the measurement systems and performance methodology that let Gimlet understand new hardware quickly, identify the limiting resource in real workloads, and turn that understanding into changes across kernels, compilers, runtimes, and distributed execution.
In the first 12-18 months, you will:
Why join now?
Gimlet is expanding from its core technology into a production neocloud spanning new hardware, customers, and data centers.
Agency Policy: Gimlet Labs does not accept unsolicited resumes from recruitment agencies or search firms. Any unsolicited resumes submitted without a signed agreement will be considered the property of Gimlet Labs, and no fees will be paid.

Gimlet Labs is an applied research lab dedicated to building next-generation AI infrastructure. Gimlet Cloud is an agentic inference cloud providing 10X faster tokens at industry-leading throughput per Watt. Gimlet's fast inference cloud is ideal for companies looking to deliver high levels of interactivity for agentic and real-time use cases. Gimlet has built the industry's first multi-silicon cloud leveraging the power of GPUs, TPUs, and SRAM-centric accelerators to disaggregate inference across the most optimized hardware for each phase of inference.