Qualcomm Semiconductor Limited
Engineering Group, Engineering Group > ASICS Engineering
General Summary:
We are seeking an experienced and innovative engineer to lead the development of MBIST diagnostics, memory repair, failure analysis, and advanced memory diagnostics flows for next-generation SoCs and advanced memory architectures.
This role spans the full cycle of memory test, diagnosis, repair, silicon debug, yield learning, and post-silicon bring-up, with strong focus on SRAM MBIST diagnostics, memory repair methodologies, failure signature analysis, and 3DIC memory diagnostics workflows.
The successful candidate will work closely with Design, Memory IP, MBIST, Silicon Validation, Product Engineering, Reliability, Yield, Packaging, and Post-Silicon teams to develop robust memory diagnostic methodologies that improve diagnosability, repair effectiveness, yield learning, product quality, and manufacturing efficiency.
This individual will serve as a technical leader and subject matter expert in MBIST diagnostics, memory repair, and 3DIC memory diagnostics, helping shape future memory-test strategies across advanced technology nodes, stacked memory architectures, and emerging multi-die systems.
【Key Responsibilities】
Memory Diagnostics & Repair
Lead SRAM MBIST diagnosis, memory failure analysis, and memory repair activities across complex SoC designs.
Analyze ATE datalogs, fail logs, MBIST fail signatures, repair data, and silicon debug results to isolate memory failures and determine root causes.
Develop and enhance memory diagnostic, redundancy analysis, BIRA, BISR, ECC, self-repair, and post-repair validation methodologies.
Define diagnostic algorithms, failure signature formats, repair flows, and data structures required for scalable memory debug.
Support investigations during HTOL failures, customer-return debug, production excursions, and high-volume manufacturing diagnostics.
MBIST Architecture & Diagnostic Methodology
Architect and implement MBIST diagnostic solutions for embedded memories, 3DIC, 2.5D, stacked memory, HBM, DRAM, and chiplet-based memory architectures across complex SoC designs.
Define MBIST controller requirements, diagnostic modes, fail capture mechanisms, error logging, and repair access flows.
Evaluate and optimize MBIST diagnostic strategies based on memory architecture, fault models, repair capabilities, and silicon debug requirements.
Influence memory design-for-diagnostics hooks, observability requirements, repair access paths, and debug infrastructure during product development.
Establish reusable memory diagnostics methodologies adopted across multiple products, technology generations, and memory compilers.
Develop end-to-end 3DIC memory diagnostics flows spanning wafer test, known-good-die validation, stack/package test, system-level validation, and post-silicon debug.
Silicon Debug & Yield Learning
Correlate manufacturing test results with silicon behavior.
Perform memory fault localization and root-cause analysis.
Support silicon bring-up, characterization, yield ramp, and production debug activities.
Develop strategies to accelerate yield learning and improve product quality.
Automation, Data Analytics & Workflow Development
Develop automation frameworks and diagnostic tools using Python, Perl, TCL, or equivalent scripting languages.
Build scalable workflows for fail-log parsing, MBIST signature analysis, repair analysis, failure classification, and diagnostic reporting.
Create data pipelines and dashboards to support yield learning, memory failure trends, repair effectiveness, and silicon debug productivity.
Apply data analytics, statistical analysis, and machine-learning-assisted techniques to improve diagnostic accuracy and yield optimization where applicable.
Standardize memory diagnostics workflows across product teams to improve debug efficiency and methodology reuse.
Technical Leadership
Provide technical leadership for MBIST diagnostics, memory repair, and 3DIC memory diagnostics initiatives across product teams.
Mentor engineers and cross-functional partners on memory diagnostics methodology, debug flows, and repair analysis.
Drive innovation and best practices in MBIST diagnostics, memory repair, post-silicon memory debug, and 3DIC diagnostics workflows.
Collaborate with EDA/IP vendors and internal methodology teams to influence future MBIST diagnostic and memory repair capabilities.
Contribute to long-term strategy for SRAM, DRAM, HBM, stacked memory, and advanced memory diagnostics technologies.
【Minimum Qualifications】
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Experience in one or more of the following: MBIST architecture, memory diagnostics, memory repair, silicon validation, post-silicon debug, yield engineering, or memory failure analysis.
【Preferred Qualifications】
MBIST Diagnostics Expertise
8+ years of experience in MBIST, memory diagnostics, memory repair, silicon validation, or yield engineering.
Deep expertise in SRAM MBIST diagnosis, fail signature analysis, memory failure classification, and repair methodologies.
Strong understanding of memory fault models, MBIST diagnostic algorithms, fail bitmap analysis, redundancy analysis, BIRA/BISR flows, ECC and self-repair architectures, memory repair validation, diagnostic data formats, and failure signature generation.
Experience developing scalable diagnostics methodologies across multiple memory compilers, memory types, products, and silicon generations.
Experience with memory diagnostics for 2.5D/3DIC, HBM, stacked DRAM, or chiplet-based architectures is a strong plus.
EDA Tool Experience
Hands-on experience with industry-standard MBIST and memory diagnostics tools such as Siemens Tessent MemoryBIST, Synopsys SMS or any other related tool.
Programming & Automation
Proficiency in Python, Perl, TCL, or equivalent scripting languages.
Experience with data analytics, machine-learning applications for diagnostics, and yield-optimization automation.
Leadership & Collaboration
Proven track record of leading technical initiatives and influencing stakeholders without direct authority.
Experience mentoring engineers and establishing best practices.
Strong communication and collaboration skills in a global, cross-functional environment.
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
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