Job Description

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About this opportunity:

Low-power RTL design often leans on established “best practices” — Gray-coded counters, clock-gated FSMs, RAM-based FIFOs, and more. These techniques are widely accepted, yet their true PPA (Power, Performance, Area) impact is rarely quantified in a controlled, isolated way. Assumptions may break under realistic parameterization, specific conditions, or different technology nodes.

In this thesis, you will deliver quantified, evidence-based characterization of common low-power RTL patterns. Instead of rules of thumb, you will systematically sweep design alternatives for the same function, measure them (including glitch power), and identify the knee points where a technique starts to pay off. You will leverage GenAI tooling to accelerate RTL variant and stimuli generation and enable broad design-space exploration. Deliverables include a reusable low-power component library, a proof-of-concept flow, and an HTML “cookbook” dashboard showing savings and trends. Results will reveal relative trends and knee points between design choices — not replace post-layout, sign-off-quality power analysis.

What you will do:

• Characterize common RTL design patterns for power (dynamic, static, glitch), performance, and area in an idealized/controlled scope.
• Build and use an Ericsson-silicon–specific analysis framework based on pre-layout netlist context, gate-level simulation (GLS) for accurate activity annotation, and glitch power analysis to capture secondary glitch contributions often missed by standard methods.
• Confirm or challenge widely held low-power assumptions with hard numbers.
• Identify knee points for savings via parametric modules (e.g., as a function of width, depth, activity).
• Create a reusable low-power RTL component library with documented savings (internal git repo).
• Cover common IP building blocks with multiple functionally equivalent variants, for example:
• Muxes (one-hot, AND-OR with registered selects, avoiding cascaded priority chains)
• Memories (per-bank enable gating, Gray-coded address pointers, validation/quantification of sleep/retention modes, entry/exit energy cost, wake-up latency trade-offs)
• FIFOs (shift-based vs. RAM-based restructuring, per-entry write gating)
• Counters (Gray-coded, LFSR, segmented high-bit counters)
• Control FSMs (clock-gated with registered one-hot selects, Gray state encoding for sequential transitions)
• Interfaces (clock-gated arbiters, balanced grant trees, crossbars)
• Package the findings into a proof-of-concept flow and an HTML dashboard “cookbook” that presents measured savings and trends.

The skills you bring:

• Master’s studies in Electrical/Computer Engineering, Computer Science, or similar.
• Background in computer architecture, ASIC design, RTL HDL coding, and testbench design using SystemVerilog.
• Working knowledge of UVM and scripting (Tcl/Python) for EDA tools is preferred.
• Curiosity to validate conventional wisdom with data, and discipline to design controlled experiments.

Why join Ericsson?

At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.

What happens once you apply?

Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.

Primary country and city: Sweden (SE) || Stockholm

Req ID: 791542