Job Description

What you'll do

Define data parallel microarchitecture satisfying ISA constraints.

Drive architecture tradeoff analysis for performance, power, area, bandwidth, latency, and scalability.

Develop and review system architecture specifications, interface definitions, and microarchitecture requirements.

Collaborate with RTL, verification, physical design, firmware, software, and system teams throughout the development cycle.

Lead performance modeling, workload analysis, and bottleneck identification using C/C++/SystemC or similar modeling environments.

Define memory hierarchy, coherency architecture, and cache structures.

Work closely with verification teams to define architectural test plans and validation strategies.

Support silicon bring-up, debug, performance tuning, and post-silicon optimization.

Contribute to long-term technology and product roadmap planning.

Job Requirements

Qualifications

Strong understanding of modern data parallel microarchitectures and subsystem integration.

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

6+ years of experience in modern data parallel microarchitecture including:

Workload characterization and profiling

Performance modeling

Out-of-order data dependency and control

Utilization / occupancy optimization

High-performance architecture design techniques

Experience with one or more of the following:

CPU/GPU/NPU architectures

NoC/interconnect architectures

Cache coherency protocols (CHI/ACE/CXL)

High-speed interfaces (PCIe, UCIe, Ethernet)

Memory systems (DDR, LPDDR, HBM, GDDR)

Power, performance, and area optimization

Strong knowledge of RTL development and verification methodologies.

Experience with architecture modeling and performance analysis tools.

Familiarity with firmware/software interaction in complex SoC systems.

Excellent problem-solving, communication, and leadership skills.