Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job responsibilities:

• Perform Product Engineering work for Genus Synthesis Solution (Genus), a logic synthesis software used for synthesizing a design described in a high-level language into logic gates, to achieve best-in-class Power, Performance & Area (PPA) for latest digital ASICs
• Understand the internal flow within the Genus for newly developed features and verify the correctness and perform experiments to determine an optimal solution
• Solve new and challenging problems in physical aware synthesis space with the goal to bridge the gap between logic synthesis and place and route
• Support the field engineers in Cadence Design Systems, Inc. and its customers in using Genus. In addition, interface between R&D and customer as the first line of support for the R&D and the customers
• Provide support to verify the interoperability of Genus with other digital logic software tools within Cadence Design Systems, Inc. to provide seamless flows
• Understand the future requirements of the software by interfacing with the internal and external customers of Genus and document the Product Requirement Specifications (PRS) for newly developed features using the standard documentation software

Preferred Qualifications:

• Experience in design and EDA with an emphasis on Cadence tools of Synthesis, Physical Design & timing closure at 20nm or below nodes
• Prior Designer, Product Engineering or Application Engineering experience in digital implementation, especially synthesis
• Understand industry challenges in digital implementation & sign off domain with exposure to 28nm & below foundry process nodes
• Industry experience with EDA tools in the IC digital implementation flow, preferably on Genus and Innovus
• Experience in Logic Design and Synthesis, Formal Verification, Low Power design, Physical Design and Timing Closure for block level and top level designs
• Automation skills using Perl, Tcl and shell scripting essential
• Knowledge of HDL – Verilog or System Verilog is preferred
• Must have logic design and timing closure skills
• Strong analysis skills required to debug complex timing closure, logical and physical design problems. Ability to perform root-cause analysis to suggest solutions to customers and provide feedback to R&D

Qualifications

• BE/BTech/ME/MS/MTech or equivalent

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