Job Description

Our vision is to transform how the world uses information to enrich life for all

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

As a DRAM Engineering Group (DEG) Design Engineer at Micron Technology, Inc., you will have ownership ofthe physical implementation of DRAM and mixed-signal circuits, translating schematics and specifications into robust, manufacturable layouts. This includes block and top-levelfloorplanning, custom layout, routing, parasitic extraction (PEX), and physical verification (DRC/LVS) to supporttapeoutreadiness. In this position you will partner closely with Circuit Design, Verification, CAD/Methodology, Process Integration, Product Engineering, Test/Probe, Assembly, and Marketing tooptimizecost, quality, reliability, time-to-market, and customer satisfaction. You will also drive layout-dependent performance improvements (area, timing, power, and yield), support silicon validation/reticle experiments, and carry out vital ECOs and final build adjustments.

Add to the layout build and physical realization of new memory products.

Interpret device and circuit specificationsand implement custom layout solutions that meet PPA (power, performance, area) and reliability targets.

Create and edit hierarchical layouts for analog, digital, and memory-array-related circuitry using industry-standard EDA tools (e.g., Cadence Virtuoso).

Develop block and top-level floorplans thatoptimizeplacement, routing resources, signal integrity, power delivery, and manufacturability.

Optimize build arrangement for critical metrics such as die size/area efficiency, matching, coupling/noise, and effects related to the arrangement that influence sense margins and array timings.

Produce layout collateral and documentation (constraints, checklists, signoff results) and relay implementation details for cross-team integration.

Physical Verification, Parasitic Extraction, andTapeoutSignoff

Run and debug physical verification flows (DRC/LVS) and drive closure using industry tools (e.g.,Calibre, Assura/PVS) and internalmethodology

Perform parasitic extraction (PEX) and collaborate with circuit designers to evaluate impacttotiming, power, noise, and functionality.

Analyze and resolve layout issues related to signal integrity, coupling/crosstalk, antenna effects, and power integrity (EM/IR) including grid and strap optimization.

Support design validation, silicon debug, and reticle experiments by performing layout fixes, ECOs, andtapeoutrevisions whilemaintainingsignoff quality.

Correlate extracted vs. silicon results andrecommendlayout changes, constraints, and rule refinements to improve yield, reliability, and performance.

Maintain Technical Expertise and Provide Training

Chip in tocross-group communication to drive standard physical design practices, reusable layout collateral, and consistent signoffmethodology

Develop andmaintainlayout documentation, checklists, andbest knownmethods (BKM) for implementation, verification, andtapeout

Participate in continuing education on advanced nodes, design rules, reliability requirements, and competitor/industry physical design trends.

Proactivelysolicitfeedback from Standards, CAD, modeling, and verification groups to ensure layout quality, tool-flow robustness, and predictable signoff convergence.

Drive innovation for future memory generations through layout-centric optimizations, automation (scripting), and improved physical design methodologies.

Manage Project Activities

Lead physical design/layout resource planning, priorities, andtapeoutschedules across multiple blocks.

Serve as the point of contact for layout implementation, physical verification, PEX/signoff, and integration issues.

Track closure of DRC/LVS/PEX/EMIR, manage risk items, and coordinate ECO execution to meettapeoutmilestones.

Prepare and communicate implementation status (QoR, signoff readiness, open issues) to technical leadership and management.

Plan and lead layout/physical signoff reviews toalign onconstraints, exceptions, and finaltapeoutdecisions.

Minimum Qualifications

7+ years of experience in the Semiconductor industry to include the following:

Bachelor's degree or equivalent experience in Electrical Engineering, Computer Engineering, or a similar area

Strong understanding of CMOS devices, VLSI concepts, and layout-dependent effects; ability to interpret schematics and design intent

Hands-on experience with custom IC layout using Cadence Virtuoso (or other IC design tools

Expertisein physical implementation andfloorplanning, including hierarchical layout, block integration, and top-level assembly

Experience with physical verification and signoff flows includes DRC/LVS and extraction of parasitic elements. Use tools such as Calibre, Assura, PVS or equivalent experience, and approved extraction engines.

Comprehensive understanding of reliability checks and layout constraints (e.g., EM/IR, antenna, ESD, latch-up) and ability to drive closure

Experience supporting DRAM sub-system physical implementation (periphery, sense amps, I/O, analog/mixed-signal, or array-adjacent circuitry) and/or high-density custom layouts

Shown experience leading technical execution across teams (design/layout/verification/CAD), driving signoff closure, and deliveringtapeuts

Experience with scripting/automation (e.g., SKILL, TCL, Python, or Perl) to improve layout productivity andsignoffturnaround time

Preferred Qualifications

Master's Degree or PhD in Electrical/Computer Engineering or related field

Excellent problem-solving and debug skills for DRC/LVS/PEX and sophisticated integration issues

Self-motivated, detail-oriented, and able to manage multiplesignoffpriorities in a fast-pacedtapeoutenvironment

In-depth knowledge of advanced-node layout considerations (DFM, patterning restrictions, density/fill, reliability rules) and memory/storage technology trends

Strong communicationskills to align constraints and tradeoffs between circuit, layout, CAD, and signoff stakeholders

5+ years of proven track record delivering custom IC layouts andtapeoutsfor DRAM (or similarly sophisticated high-density designs)

"The specified role does not encompass the following responsibilities: Finalization of sales agreements or the execution of sales contracts is prohibited. The role also does not carry the authority to make definitive decisions regarding contracts, be it their conclusion or termination. Furthermore, the role is not designed to involve participation in pricing negotiations or the authorization of contracts. These activities fall beyond the permissible duties of the position."

We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.

To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_na@micron.com

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.

AI alert Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.

Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.