LEADICLAYOUTENGINEER– Joint Development Team

The Group 

The Joint Development Team (JDT) is a small, independent, cross-disciplinary group whose charter is to accelerate the development of key components, systems, algorithms, and techniques necessary to advance the state of the art in targeted areas and to collaborate with focused product development teams to get these advances to the marketplace. Current and future research areas include advanced medical devices, energy metering and fault detection, high-speed imaging, security electronics, ultra-precision references and data converters. 

The group is led by Analog Devices Fellow JED Hurwitz, a pioneer in CMOS imaging, recognized expert in ultra-high precision, and of broad industrial experience. The group culture aims to foster a challenging, exciting, and supportive environment. 

The team members must be comfortable working on a wide variety of products and technologies in a fast-paced and agile environment and will be exposed to various groups across the corporation’s many sites through all stages of the development cycle. 

JDT is expanding its presence in the Philippines

Analog Devices’ Joint Development Team (JDT) is growing its footprint in the Philippines to enable complete front‑end productdevelopment, from architecture through first silicon.We are expanding across analog, digital, verification, and layout disciplines to support advanced mixed‑signal products in precision sensing, imaging, and security applications.This expansion represents a long‑term investment in senior technical talent and leadership roles within ADI Philippines.

The Role

The P4Lead IC LayoutEngineeris a senior technical leader responsible for driving complex IC layout development within JDT. This engineer owns layout strategy for advancedmixedsignalproducts, influencesfloorplanningand architecture decisions, and serves as the primary layout authority on programs. The role has broad technical scope, high autonomy, and visible impact across projects.‑signal products, influences

This position is intended for candidates with demonstrated leadership, deep technical expertise, and the ability to raise the overall capability of the layout discipline.

KeyResponsibilities: 

• Lead and own complex IC layout developments, includingsectionlevelandtoplevellayouts with full accountability for quality and schedule ‑level and top‑level layouts with full accountability for quality and schedule

• Develop innovative solutions to complex layout challenges requiring deep technical analysis and expertise

• Influence IC architecture,floorplanning, and partitioning decisions in collaboration with various disciplinedesign teams

• Serve as the primary technical mentor forP1–P3layout engineers; perform reviews and capability development

• Drive improvements in layout methodologies, design standards, and best practices across projects

• Represent layout engineering incrossfunctionalandprogramleveltechnical discussions‑functional and program‑level technical discussions

Minimum Qualifications

• BS/MS in Electrical or Computer Engineering (or equivalent experience)

• ~7+ years of IC layout experience on complex analog/mixed‑signal products

• Expertlevelproficiencyin CMOS layout, parasitic management, reliability, andmanufacturability ‑level proficiency in CMOS layout, parasitic management, reliability, and

• Strong leadership and influence skills across design, DV, and systems teams

• Excellent communication, mentoring, and technical documentation skills