Job Description

Looking for Lead Design Verification Engineers with 6+ years of experience who will be responsible for pre-silicon verification of IPs, subsystems, and SoC designs to ensure functional correctness and high-quality silicon delivery.
Develop and execute comprehensive verification strategies, UVM-based environments, and coverage-driven verification plans to achieve verification closure. Collaborate with architecture, design, firmware, and software teams to validate RTL implementation against specifications and micro-architecture requirements.

Job Qualification:
• Bachelor's Degree in Electrical Engineering (EE) or Master's Degree in Electrical Engineering (EE).
• More than 6 years of hands-on experience in Digital Verification within a reputed semiconductor design company.
• Strong understanding of SoC architecture, digital design, and computer architecture concepts.
• Proven experience in RTL verification using Verilog and SystemVerilog.
• Strong expertise in Universal Verification Methodology (UVM) and coverage-driven verification techniques.
• Experience in developing verification plans, testbenches, scoreboards, assertions, and constrained-random verification environments.
• Good knowledge of functional coverage, code coverage, regression management, and verification closure methodologies.
• Experience with industry-standard simulators such as VCS, Questa, and Xcelium.
• Hands-on experience verifying protocols such as I2C, I3C, SPI, AXI, PCIe, USB, Ethernet, or similar interfaces.
• Proficiency in scripting languages such as Python, Perl, Tcl, or Shell scripting for automation and debug.
• Strong debugging and problem-solving skills with attention to detail.
• Ability to analyze specifications and identify functional gaps, corner cases, and verification risks.
• Good verbal and written English communication skills.
• Ability to work effectively in cross-functional and global engineering teams.
• Self-motivated team player with a strong commitment to quality and timely project execution.

Job Responsibility:
• Responsible for the pre-silicon verification of IP modules, IP subsystems, and/or SoC top-level designs.
• Define digital verification strategy, verification architecture, and execution plans for SoC and subsystem-level verification.
• Develop, maintain, debug, and execute UVM-based verification environments for RTL and gate-level simulations.
• Create directed and constrained-random test cases, stimulus generators, scoreboards, checkers, and assertions.
• Execute simulation regressions, analyze failures, and drive bug tracking and resolution to closure.
• Collect, analyze, and drive code coverage, functional coverage, and assertion coverage metrics to achieve verification sign-off.
• Interface with Hardware, Firmware, Software, Architecture, and System Engineering teams to ensure complete specification coverage.
• Verify industry-standard interfaces and protocols such as I2C, I3C, SPI, AXI, PCIe, USB, Ethernet, and other high-speed interfaces.
• Utilize industry-standard EDA tools such as Synopsys VCS, Siemens Questa, and Cadence Xcelium for verification and debug activities.
• Contribute to verification methodology improvements, automation, scripting, and best practices to enhance team productivity and quality.

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