Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Member of the Tensilica team within Cadence, responsible for design and verification of emerging hardware products as part of families of Tensilica cores.

Perform the role of verification engineer of some features of processor cores under development. Understand architecture and micro-architecture of processors under development and take ownership of verification effort. This will include creating detailed test plans, new verification infrastructure and execution.

RESPONSIBILITIES:

• Verification ownership of a feature from start to finish. Define and develop detailed test plans, execution, sign off
• Develop System Verilog/UVM testbench and infrastructure.
• Apply formal verification methodology for verification sign off and quality.
• Develop and apply novel verification techniques for verifying performance of designs.
• Collaborate with design team to understand the micro-architecture and pipeline.

Position Requirements:

• Strong knowledge of computer architecture, especially processor pipeline and vector processing.
• Knowledge of DSP arithmetic functions.
• Exposure in hardware verification concepts such as assertions, scoreboard, coverage.
• knowledge in Verilog, System Verilog and UVM.
• Familiarity of AI in Design and DV is preferred
• Familiarity with performance modelling and verification including benchmarks.
• Understanding and basic proficiency in C or C++
• Proficiency in any scripting language (Python or Perl preferred)
• Familiarity with source code control (Git/Perforce)
• Ability to work efficiently with remote teams in different time zones
• Ability to work successfully both independently and in a team environment
• Strong problem-solving skills, flexible, adaptable and proactive
• Strong communication skills
• MSEE, MSCE.
• MS and 2 years of working in a design or verification role

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