Job Description

Lead ASIC RTL Design Engineer — Remote (U.S.) - No visa sponsorship

Our client, a leader in AI Compute is seeking a senior-level ASIC design engineer to drive the development of high-performance silicon components used in advanced compute platforms. This individual will take ownership of key IP blocks from early architectural definition through RTL delivery and signoff, working closely with cross-functional teams to meet aggressive performance, power, and area goals. The role combines hands-on design work with technical leadership and mentorship.

Core Responsibilities

Architecture & RTL Development

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  Define microarchitecture for complex subsystems and document design specifications
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  Implement high-quality, reusable RTL in System Verilog with clear interface definitions and design intent
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  Incorporate assertions and design-for-debug features within RTL

Design Ownership & Implementation

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  Lead front-end design activities including linting, clock/reset domain analysis, and synthesis readiness
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  Collaborate with physical design teams on floor planning, timing closure, and implementation tradeoffs
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  Take responsibility for achieving performance, power, and area (PPA) targets for assigned blocks

High-Speed Interfaces & Memory Systems

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  Design and integrate high-bandwidth interfaces and interconnects (e.g., AMBA-based protocols, coherent fabrics)
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  Work on memory subsystem integration, including external DRAM and high-throughput memory solutions
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  Coordinate with internal teams and third-party IP providers to ensure proper integration and functionality

Engineering Processes & Tooling

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  Establish and maintain RTL design standards, reusable components, and signoff criteria
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  Contribute to automation and workflow improvements using scripting and build systems (Python, Tcl, CI pipelines)

Collaboration & System Integration

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  Partner with verification teams on test planning, coverage goals, and model alignment
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  Work with architecture and performance engineering to validate design intent against system-level expectations
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  Support silicon bring-up, debugging, and downstream customer or system integration efforts

Technical Leadership

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  Mentor less experienced engineers and provide guidance on design best practices
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  Lead design reviews and help drive key technical decisions across teams
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  Advocate for scalable, efficient, and high-quality engineering solutions

Basic Qualifications

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  Bachelor's or Master's degree in Electrical or Computer Engineering (or similar field)
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  8+ years of experience in ASIC or SoC RTL design for complex, high-speed devices
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  Demonstrated experience delivering designs from concept through RTL implementation and tape out readiness
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  Strong System Verilog expertise, including clocking strategies, reset design, and domain crossing considerations
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  Hands-on experience with front-end design tools and flows (linting, CDC analysis, synthesis, timing analysis, DFT)
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  Familiarity with multiple high-speed technologies such as memory interfaces, interconnect protocols, or compute data paths
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  Strong communication skills with the ability to lead technical discussions and document designs clearly

Preferred Experience

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  Exposure to AI/ML hardware or high-performance compute architectures
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  Knowledge of formal verification techniques and assertion-based design
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  Experience with power optimization methods (e.g., clock gating, power intent formats like UPF/CPF)
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  Familiarity working alongside verification environments (UVM, Python-based frameworks, or similar)
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  Understanding of modern processor subsystems, coherence models, or custom tool flows