• To provide key technical support in digital IC design implementation product demonstration, and sales presentations.
• To demonstrate strong ability and to be hands-on in full APR flow including floorplan, placement, timing analysis, CTS, signoff timing and PV closure methodology.
• To support key customer engagements on the business increase.
• Have real design tape-out experience especially (nice to have) for advanced node design.
• To play a leading role among other team members, while receive little instruction on routine and general assignments
Position Requirements:
• Master better with 3+ years working experience or Bachelor better with 5+ years’ experience in IC design. (Cadence Innovus experience will be a plus)
• Familiar with full APR flow including both logical + physical related (timing, SI , congestion , routing drc , hier design ....etc .) and MSV knowledge + methodology.
• Good communication in English and Chinese, good confidence and good attitude and self-motivation .
• Be familiar with shell/perl/tcl etc. script language.
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.
