Job Description

About the company

Our client is a technology company.

The role

Raydar is recruiting for this role on behalf of our client. This engineer works on speeding up computation across machine learning work, from experimentation through to running models for end users. Much of the day goes into crafting low-level code for dedicated chips, along with advising model developers on how their proposed changes will affect speed and cost.

What you'll do

• Hand-write and tune low-level compute code for dedicated chips.
• Track down slowdowns in training and serving pipelines and remove them.
• Explain to model researchers how proposed architecture changes will affect runtime.
• Benchmark changes rigorously to confirm real gains in speed and memory use.

Requirements

What we're looking for

• Five or more years of practical engineering experience in a technical field, typically alongside a bachelor's degree in computing or electronics, or an equivalent track record in practice.
• Strong command of core operating system concepts such as scheduling, concurrency control and memory management.
• Familiarity with how CPUs and GPUs are organized, and with designing hardware and software together.
• Practical fluency with a major deep learning framework and the algorithms behind modern models, applied to engineering problems.
• Skill at measuring how computation and memory are used and pinpointing what holds a system back.
• A track record of creating compute routines for machine learning chips used in language model training or serving.
• Comfortable writing performance-critical code in C or C++.
• Experience tuning speed with low-level hardware metrics, small targeted tests and profiling tools.
• Working today at a staff-equivalent level, owning low-level software for a chip or compiler group.
• Academic grounding in computer hardware design, through an engineering degree or graduate study in architecture.

Bonus points

• Current work on an accelerator or chip team.
• Back-end compiler experience, such as code generation, lowering and hardware scheduling.
• Background spreading large model jobs over groups of linked chips.
• Familiarity with compiler and toolchain internals and with ML framework internals.

Benefits

Compensation and benefits

• Base salary: USD 350,000 to 450,000 per year
• Equity
• Competitive benefits

Location and work model

• San Francisco, CA, United States
• On-site
• 5 days in-office per week
• Full-time