IP Verification Engineer
职位描述
Responsibilities
1. Participate in the development and verification of core IP modules.
2. Plan verification strategies, develop verification plans based on product features, and decompose test points.
3. Build testbenches using SystemVerilog/UVM, develop test cases, and drive coverage convergence.
4. Complete IP functional, performance, and power verification; support SoC integration verification and gate-level simulation.
5. Support verification activities during architecture design, RTL coding, and prototype development.
6. Build and manage the verification team, leading the team to achieve successful IP tape-out and delivery (for Staff level).
职位要求
Requirements
1. Solid academic foundation in digital circuits, integrated circuits, signals and systems, linear algebra, computer architecture, and C programming.
2. Familiar with digital IC design and development flows.
3. Proficient in Verilog RTL coding and testbench development for simulation.
4. Good understanding of AXI, CSI, MIPI, and other related protocols.
5. Good understanding of image formats and image processing algorithms.
6. Strong programming and debugging capabilities.
7. Familiar with mainstream verification methodologies (UVM, SVA, etc.).
8. Capable of independently completing full-cycle verification of a brand-new module from scratch.
9. 3–10 years of experience in the verification industry (Senior: 3–5 years; Staff: 6–10 years).
Preferred Qualifications
- Experience in IP or SoC verification for vision processing, image processing, or ADAS.
- Experience in FPGA or emulator development and debugging.
- Familiar with formal verification tools (FPV/DPV).
- Good understanding of neural network algorithms.
- Familiar with CPU, GPU, and NPU architectures and instruction sets.
- Experience in parallel computing and acceleration IP development.
- Proven experience in leading teams and delivering complete IP projects (for Staff level).
- Experience in leveraging AI to assist and accelerate verification, automating flows, and improving verification efficiency and quality.
投递
