Job Description

Summary

As IP Logic Design Engineer, you will combine RTL implementation and Micro-Arch. You work at the center of a PHY design effort collaborating with architecture, analog, CAD, timing and PD design teams, with critical impact on delivering elite PHY designs. You will collaborate with the engineering design team to develop the verification environment for block and SoC developments. Join us and participate in the architecture of next generation PHY.

At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for an exceptionally talented Design Verification Engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day.

The position is relevant to all Apple sites: Herzliya, Haifa and Jerusalem

Description

In this role, you'll participate in the architecture of next-generation PHY, conduct RTL implementation of the micro-architecture, and participate in clearly defining specification, testing, and verification of the PHY design.

Work in collaboration with CAD, PD teams to implement RTL design into GDS, run various design verification flows and provide guidelines to other designers, and participate in establishing CAD and design methodologies for correct-by-construction designs

Preferred Qualifications

Team player with excellent communication skills and the desire to take on diverse challenges

Minimum Qualifications

B.Sc or M.Sc Electrical Engineering or Computer Engineering

8+ years of Logic Design experience

Experience developing and implementing AMS PHY

Advanced knowledge of standard ASIC verification flows, including simulation and testbench development

Knowledge about industry standards in PHY Design, including RTL writing and verification tools of RTL

Deep Understanding of all aspects of PHY construction, Integration, and Physical Design

Working knowledge of Extraction and STA methodology and tools

Excellent knowledge of System Verilog, Verilog

Good knowledge of C / C++

Experience with either Perl/Tcl scripts

Knowledge of industry standard interfaces and experience with multiple frontend simulators/debuggers

Deep understanding of Design methodology to debug issues at PHY level

A teammate with excellent interpersonal skills and the desire to pursue diverse challenges