Job Description

Job Details:

We are seeking a skilled IP Design Verification Engineer to join our team and play a critical role in ensuring the functional integrity of our intellectual property designs. This position involves comprehensive verification of IP logic blocks, development of robust verification environments, and collaboration with cross-functional teams to deliver high-quality silicon solutions.

Key Responsibilities:

• Perform comprehensive functional verification of IP or subsystem logic blocks to ensure compliance with specification requirements
• Develop and execute detailed verification plans, test benches, and verification environments with comprehensive coverage metrics
• Oversee development of UVM-based testbenches, constrained-random stimulus, and coverage closure
• Identify, replicate, and debug issues in presilicon environments using advanced debugging methodologies
• Implement corrective measures and resolution strategies for failing test cases and verification scenarios
• Collaborate closely with system architects, RTL design engineers, and physical design teams to enhance verification of complex architectural features
• Document comprehensive test plans and facilitate technical reviews with design and architecture stakeholders
• Maintain and continuously improve existing functional verification infrastructure, tools, and methodologies. Ensure compliance with industry-standard verification practices and maintain high-quality standards.
• Demonstrate innovation in verification processes, including AI/ML-driven verification or developing custom automation scripts. Evaluate new verification technologies and incorporate them to continuously improve efficiency and effectiveness.
• Ensure verification completeness across all IP functional domains. Partner with cross-functional teams to ensure seamless integration and verification sign-off.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualification:

• 7+ years of experience in developing System Verilog & UVM based testbench for IP, subsystem or SoC level validation.
• Experience with verification tools such as Synopsys VCS, Cadence Xcelium, or Mentor Questa
• Experience with creating directed and random test cases and developing/maintaining test plans.
• Experience with design verification and validation methodologies and strategies.
• Experience with version control systems (Git, Perforce)

Preferred Qualifications:

• Proficient in validating and debugging NOC, Data path, Interconnects, Clock and resets, Power management designs.
• Formal verification techniques
• Power-aware verification and low-power design verification
• CPU/GPU architecture and microarchitectural verification
• Continuous integration and regression management systems

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Business group:

At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.