Job Description

About Altera

At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

About the Role

Join Altera IP solutions team and work on cutting edge FPGA RTL and IP design!  Altera's IP Solutions Engineering (IPSE) team develops comprehensive solutions to provide customers easy and efficient access to the capabilities of Altera’s FPGA devices. These solutions are provided as highly configurable intellectual property (IP) cores that are fully integrated with Altera's software CAD tool, Quartus Prime. The External Memory Interfaces (EMIF) team is responsible for developing IPs for communication with state-of-the-art DDR and LPDDR devices. The ever-growing demand for faster and higher-density memories - especially in the data center and machine learning sectors - presents a challenging design problem that requires system-level knowledge of silicon, software, IP, and customer applications.

You will work with a team of engineers to develop and verify state-of-the-art External Memory IP cores for interfacing with DDR5 and LPDDR5 memories. You will be working on advanced FPGA architectures, design definition, implementation, and verification. Additionally, you will also be developing design examples and simulation models, accompanied by a rich set of technical documentation. In this role, you will work closely with multiple teams, including silicon design and validation, post-silicon validation, application engineering, and customer experience teams, to ensure seamless development, integration, and optimization of high-speed interface IP solutions.

Your specific responsibilities will include, but are not limited to the following:

• Architecture and Design based on the latest protocol specifications for DDR and LPDDR devices

• RTL development

• Device support and CAD tool integration

• Verification (e.g. verification IP, methodologies, frameworks, bus functional models, regression tests)

• Hardware power-on and debug

• New product release and rollout support

• Customer technical support

The candidate should possess the following behavioral traits:

• Strong skills in communication, initiative, innovation, and teamwork

• Highly motivated to learn and adapt to fast-changing technologies and environments

• Excellent problem-solving skills and attention to detail

• Demonstrate fundamental values such as accountability, integrity, and a winning mindset

• Collaborative mindset, strong influencing skills, and a willingness to work across geographical locations

Salary

Qualifications:

You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• Currently pursuing a BS degree in Computer Engineering, Engineering Science, Electrical Engineering, Computer Science or related field

• 3+ months of experience in Digital logic hardware (e.g. SystemVerilog, Verilog and/or VHDL) design or verification

• 3+ months of experience in scripting languages and/or software programming (e.g. Python/TCL/Perl and/or C/C++)

Preferred Qualifications:

• FPGA design experience

• Experience with RTL simulation, timing closure and static timing analysis

• Experience with DDR and/or LPDDR hardware interfaces

Job Type:

Student / Intern (Fixed Term)

Shift:

Shift 1 (Canada)

Primary Location:

Toronto, Ontario, Canada

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.