Job Description

Huawei’s vision is to enrich lives through communication and intelligent innovation.

As a global leader in information and communications technology (ICT), Huawei drives innovation in artificial intelligence, cloud computing, and smart device technologies. Through its Carrier, Enterprise, and Consumer business groups, the company delivers advanced Network Infrastructure, Cloud and AI Platforms, and industry-leading devices.

Huawei supports 45 of the world’s top 50 telecom operators and serves one-third of the global population, with operations in over 170 countries and a workforce of more than 200,000 employees.

Huawei Technologies Switzerland AG contributes to this innovation through cutting-edge research, with offices in Zurich and Lausanne focusing on High-Performance Computing, Computer Architecture, Computer Vision, Robotics, Artificial Intelligence, Neuromorphic Computing, Wireless Technologies, Networking, and related fields.

In this job opening, we are seeking a highly motivated and visionary researcher to join our team focused on chiplet-based computing systems. This role involves research and development in chiplet-based architectures, aiming to overcome performance and scalability limits of traditional compute platforms.

Responsibilities:

• Conduct cutting-edge research on the co-design of communication and computation for wafer-scale systems. On the communication side, the work focuses on architecting Networks-on-Chip, providing scalable, high-bandwidth, and ultra-low-latency interconnects that efficiently span multiple dies and support fine-grained data movement. On the computation side, the research emphasizes optimizing and mapping training and inference workloads to fully exploit wafer-scale resources, improving performance, scalability, and energy efficiency through intelligent task placement and scheduling.

• Investigate various aspects of system design, including:

- Network-on-Chip design, further including Topology exploration, routing algorithms, and protocol/flow-control design to support high-throughput collective communication, low-latency synchronization, and efficient model/data parallelist

- Expressing and Mapping LLM Parallelism to Wafer-Scale System that simplify LLM parallelism (e.g., tensor, pipeline, and data parallelism) and efficiently map training and inference workloads onto wafer-scale system

Requirements:

• Master in Electrical Engineering, Computer Engineering, Computer Science, or a closely related field.

• Background in interconnection networks and computer architecture is a must.

• Demonstrated research expertise in one or both of the following areas:

- Network-on-Chip (NoC) architecture, including routing, flow control, topologies, and performance modeling

- LLM parallel execution and co-design, including workload decomposition, communication–computation overlap, and mapping to high-performance interconnects

• Excellent analytical, problem-solving, and system-level thinking skills.

• Excellent programming skills with hands-on experience in simulator modeling, development and simulator-based evaluation.

• Strong verbal and written communication skills, and the ability to work both independently and collaboratively in a cross-disciplinary team.

Why join us:

• Collaborate with world-class scientists and engineers in an open, curiosity-driven environment;

• Access to state-of-the-art technology and tools;

• Opportunities for professional growth and development;

• Competitive salary, and a high quality of life in Zurich, at the center of Europe;

• Last but certainly not least: be part of innovative projects that make a difference.