Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Design Systems Inc. is looking for a motivated Intern: Application Engineering - Silicon Signoff and Verification to work with us in Belo Horizonte, Brazil. At Cadence, we hire and develop leaders and innovators who want to impact the world of technology. Cadence has been nominated as a Great Place to Work globally and in Brazil and is also a Fortune 100 Best Companies to Work For

As an Intern: Application Engineering - Silicon Signoff and Verification, you will be part of the Silicon Signoff and Verification (SSV) team. The SSV team works with the Quantus, Pegasus and Voltus platforms. To understand more on what we do, you can visit here Working at Cadence is very dynamic, fast-paced, and integrated with other teams all around the world.

• The Candidate will be trained on the Cadence tool set, in the context of multiple flows for Integrated Circuit (IC) Physical/Signoff, Parasitic Extraction, full-chip electromigration, IR drop and power analysis to support our leading-edge customers meet/exceed their signoff targets, achieve faster design closure, and turn their design concepts into reality. Using Cadence’s suite of tools, you will help develop creative and innovative solutions for customers, benchmark product capabilities for a wide range of flow regimes and phenomena, advocate for best practices, and collaborate with members of the sales and product teams.

Key responsibilities in this position are to:

• Helping customers to adopt and proliferate our IC Signoff solutions
• Conducting technical presentations, technical training, and product demonstrations, including development of customized presentations
• Supporting technical evaluations and benchmarks
• Help R&D and product engineers develop competitive and creative technical solutions

Minimum Requirements

• Enrollment in a BS in Electrical, Electronics, System Engineering, computer science or related areas on progress.
• One year to graduate (Max: 6/2027).
• Excellent written and verbal communication skills
• Interest in learning new technologies
• Open to continued personal development to meet the evolving demands of the EDA industry

Nice to have skills - University contact:

• Knowledge of MOS transistors
• Previous exposure to Physical verification flows ( i.e.. DRC, LVS & FILL), Parasitic extraction flows or IR Drop/Electromigration tools
• Physical verification rule writing or in parasitic extraction is a plus
• Familiarity with Cadence Implementation tools (Innovus, Virtuoso, Allegro/APD) or similar industry tools
• In-depth understanding of Semiconductor Manufacturing process is a plus
• Programming skills like Linux, Python, Bash, Tcl or Perl is a plus. Self-motivated and enthusiastically focused on problem solving
• Team player with a positive attitude, willingness to offer and execute ideas and solutions to enhance processes within an evolving environment

Additional Job Details:

• Internship term: 20 hours/week
• Location: Av. do Contorno, 5800, Savassi - Belo Horizonte

About Cadence Design Systems:

Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. For more information, access http://www.cadence.com

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