Job Description

NextSilicon is reimagining high-performance computing. Our accelerated compute solutions leverage intelligent adaptive algorithms to vastly accelerate supercomputers, driving them forward into a new generation. Our new software-defined hardware architecture enables HPC to fulfill its promise of breakthroughs in all fields of advanced research.

At NextSilicon, everything we do is guided by three core values:

• Professionalism We strive for exceptional results through professionalism and unwavering dedication to quality and performance.
• Unity Collaboration is key to success. That's why we foster a work environment where every employee can feel valued and heard.
• Impact We're passionate about developing technologies that make a meaningful impact on industries, communities, and individuals worldwide.

NextSilicon is looking for a talented and experienced engineer to play a crucial role in the physical design implementation of the company’s next SOC. As a Senior Physical Design Engineer you will be responsible for the physical implementation of digital designs in semiconductor technologies, from RTL to GDSII. This position involves optimizing the layout, power, and performance of ICs, ensuring they are ready for manufacturing and meet stringent design requirements. The role requires close collaboration with cross-functional teams, including front-end designers, verification engineers, and product teams, to create high-quality, manufacturable designs.

Requirements

• 4 to 5 years of experience in physical design for semiconductor devices, with proven expertise in Floorplanning , Placement , Clock Tree Synthesis , extraction and timing closure
• Will be responsible for executing the block level place and route assignments from RTL through GDS
• Hands-on experience with EDA tools like Synopsys Fusion Compiler , ICV , PT and Mentor Calibre
• Develop and maintain automation scripts to streamline Physical Design tasks
• Will be responsible to work with design teams to drive the analysis for timing closure
• Proficient in power analysis and power management techniques
• Good understanding of process technologies and design rules
• Excellent problem-solving skills and attention to detail
• Ability to work in a fast-paced environment and meet deadlines

Responsibilities

• Perform synthesis, floorplanning, placement, clock tree synthesis (CTS), and routing of IC designs at block and Sub-system level
• Convert high-level RTL (Register Transfer Level) code into a manufacturable silicon layout while meeting PPA goals, both at Block and Sub-system level
• Analyze and resolve issues related to power distribution, signal integrity, and noise
• Ensure designs meet all design rules and verify the physical layout against the logical schematic. Be able to resolve all DRC and LVS issue in their designs
• Work with subsystems and full chip teams to drive physical verification.
• Provide Automation solution for faster convergence
• Utilize EDA (Electronic Design Automation) tools such as Synopsys, and Mentor Graphics for design implementation.
• Work closely with RTL design, verification, and DFT (Design for Test) teams to address design challenges and ensure integration of all design components.
• Ability to implement solutions and troubleshoot complex problems with limited or no supervision