Job Description

The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technologies to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.

The FPGA/ASIC Design team and Verification team work in close collaboration, pushing boundaries in low-level computer architecture, logic design, tool writing, and the interface between hardware and software. There is often overlap in skills, and both teams work together very closely. The Hardware Engineering Summer 2027 Internship offers candidates the opportunity to explore both Design and Verification roles.

During HRT’s Hardware Engineering Internship, you will have the opportunity to create hardware in SystemVerilog (design) and build complex modeling and testing environments in Python (verification). You can always expect to be challenged by the ever-changing financial markets, and find yourself working on critical infrastructure in an extremely fast-paced, real-time environment.

What to Expect

• A challenging and meaningful summer internship program that will give you an introduction to all technical facets of hardware engineering in the algorithmic trading industry
• Independent projects that will have you deep dive into our hardware design and verification environments
• An opportunity to work with and learn more about cutting edge FPGA/ASIC technology
• After some intense but brief training, you’ll jump right into projects within your first two weeks of the program
• You'll learn all about HRT's research and trading infrastructure, even in areas you won’t be working in
• You’ll have the opportunity to learn about and gain a deeper understanding of the financial markets

Requirements

• You are a full-time student in a Computer Engineering, Electrical Engineering or related program
• You will be graduating and looking for full-time roles in 2028
• A thorough understanding of digital logic design and/or computer architecture
• Experience using a hardware design language such asSystemVerilog
• Familiarity with C++ and/or Python
• Knowledge of Linux and familiar with its command prompt
• A passion for technology and curiosity for how things work “under the hood”
• Exceptional problem solving skills
• Bonus: Familiarity with FPGAs or ASICs
• Bonus: Exposure to a hardware verification flow such as UVM, or open-source verification tools such as cocotb

We do not allow multiple applications. Please apply to the ONE role you are most interested in and we will consider you for all open positions when reviewing your application.

Weekly base salary of 5,800 USD and a competitive signing bonus in addition to company-paid housing, meals, and other perks.