Job Description

We are seeking a highly motivated Design Verification (DV) Engineer to verify Design-for-Test (DFT) and test-related logic for complex SoC and IP designs on our flagship FPGAs. The successful candidate will be responsible for developing and executing comprehensive pre-silicon verification plans, creating UVM-based testbenches, and ensuring high-quality silicon through rigorous verification methodologies.

Key Responsibilities

• Develop and execute verification plans for DFT and test logic features, including scan, MBIST, LBIST, JTAG, boundary scan, and related infrastructures.
• Create and maintain SystemVerilog/UVM-based verification environments.
• Develop reusable verification components, sequences, scoreboards, assertions, and coverage models.
• Verify DFT architectures and test modes at IP, subsystem, and SoC levels.
• Perform functional, regression, and coverage-driven verification.
• Analyze simulation failures, debug RTL and testbench issues, and drive root cause resolution.
• Collaborate closely with DFT architects, design engineers, validation teams, and physical design teams.
• Review specifications and provide feedback on testability and verification requirements.
• Track verification metrics, functional coverage, code coverage, and regression results.

Qualifications:

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 5+ years of ASIC/SoC design verification experience.
• Strong expertise in SystemVerilog and UVM methodology.
• Experience verifying DFT features such as:
  • Scan insertion and scan compression
  • MBIST
  • LBIST
  • JTAG / IEEE 1149.x
  • Boundary scan
  • Test access mechanisms
• Strong debugging skills in simulation environments.
• Experience with industry-standard simulators such as VCS, Xcelium, or Questa.
• Knowledge of assertions (SVA), constrained-random verification, and coverage-driven methodologies.

Preferred Qualifications

• Experience with SoC-level verification.
• Familiarity with ATPG concepts and test pattern generation.
• Knowledge of low-power verification methodologies.
• Experience with scripting languages such as Python, Perl, or Tcl.
• Understanding of CI/CD and automated regression environments.
• Experience mentoring junior verification engineers.

Technical Skills

• SystemVerilog
• UVM
• SVA
• DFT Architectures
• Scan/MBIST/LBIST/JTAG
• Functional Coverage
• Regression Automation
• Python/Perl/Tcl
• Git or equivalent version control systems

Desired Traits

• Strong analytical and problem-solving skills and attention to detail.
• Excellent communication and collaboration abilities.
• Ability to work effectively in a fast-paced development environment.
• Self-driven with a focus on quality and execution.
• Demonstrate fundamental values such as accountability, integrity, and a winning mindset

Job Type:

Regular

Shift:

Shift 1 (Malaysia)

Primary Location:

Penang 15, Penang, Malaysia

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.