We areseekinga highly motivated intern currently pursuing or holding aMaster'sdegree in Electronics or Computer Engineering with a specialization in VLSI. The ideal candidate willpossessfoundational knowledge of VLSI design and validation, withadditionalexperience in high-speed design challenges seen asadvantageous ThisPositionprovidesan exciting opportunity to engage directly with post-silicon system validation activities for next-generation Altera FPGA products, specifically focusing on high-speed transceiver protocols.
Key Responsibilities:
FPGA IP Design &Validation using Verilog.
Support the FPGA post-silicon system validation group in ongoing and upcoming projects or newmethodologyinitiatives.
Assistin the development and implementation of innovative validation and debugging solutions.
Document technical specifications clearly andmaintainorganized records of project progress.
Collaborate closely withvalidationteam members to understand and improve workflows and methodologies.
Prepare and present updates and findings to stakeholders asrequired
Skills and Qualifications:
7+ years of experience in Semiconductor IP Design.
Familiarity with HDL languages (VHDL, Verilog,SystemVerilog).
Experience or knowledge in scripting languages such asTcl, Perl, or Python.
Prior experience or exposure to FPGA tools (Quartus orVivado) would beadvantageous
Strong willingness to learn new skills and technologies.
Ability to work collaboratively within a team environment.
Good communicationskills and ability to clearly present project details and outcomes.
Regular
Shift 1 (India)
Bengaluru, Karnataka, India
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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