Job Description

ASIC Firmware Engineer.

Firmware Engineer — AI ASIC Accelerator

We're looking for an experienced Firmware Engineer to build the low-level software foundation for our next-generation AI training ASIC. In this role, you'll implement the secure boot chain, hardware bring-up sequences, runtime management, and host communication protocols that bridge custom silicon and AI workloads. You'll collaborate with silicon architects, Linux driver engineers, security teams, and system validation to deliver production-grade firmware for enterprise AI infrastructure.

Experience necessary to do the following:

• Implement secure boot chain (BootROM → PBL/SBL → RTOS), device attestation, and field update mechanisms
• Bring up clocks, power domains, HBM, PCIe, NoC, and high-speed SerDes PHYs on emulation/FPGA and silicon
• Configure 400G Ethernet interfaces (MAC/PCS/FEC) and coordinate with network stack for RDMA offload
• Develop runtime services: power/thermal control, DVFS, watchdogs, RAS (ECC, crash dumps), error recovery
• Design mailbox protocols, MSI/MSI-X handling, and DMA coordination with Linux driver team
• Build unified telemetry and event tracing with synchronized timestamps (PTP/PHC)
• Support multi-die discovery, link training, and topology management for chiplet scaling

What We're Looking For:

• 5+ years embedded firmware (C/C++/Rust) on ASIC/SoC or GPU-like accelerators
• Proven experience with PCIe bring-up, HBM/DDR subsystems, or 100G+ Ethernet — at least one is a must
• Hands-on with clock/power domain configuration and RAS features
• Comfortable with schematics, register specs, JTAG/logic analyzer debugging
• Strong documentation habits and systems thinking across the full stack
• RISC-V/ARM64, TrustZone/TEE, secure provisioning, or QEMU pre-silicon experience is a plus
• Familiarity with requirements traceability is valued