Job Description

The Foundational Security team (FST) is looking for digital logic designers keen to work on a scalable IP design. Candidate will be responsible for design and validation of new IP roadmap features as part of FST's HW IP developing HW security for various market segments across Intel. As a member of the team, the candidate would be responsible for driving scalable IP development while also making the Design Integration and SOC delivery a fully automated solution. Candidate will be part of an IP team working closely with other verification engineers, RTL design engineers, micro-architects, and other team members in determining the proper implementation strategy for new design, ensure quality of design, and develop test-plans, verification environment, and drive delivery to SoC. They will have an opportunity to learn and contribute towards making Intel Hardware more secure.

The primary responsibilities for this role will include, but are not limited to:

• Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
• Participates in the definition of architecture and microarchitecture features of the block being designed.
• Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
• Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
• Supports SoC customers to ensure high-quality integration and verification of the IP block.
• Drives quality assurance compliance for smooth IPSoC handoff.
• Excellent communication and organization skills are critical, along with teamwork, and must demonstrate strong technical skills, along with having passion for design or validation.
• Must have strong orientation for Quality and Commit and Deliver and Drive Innovation/efficiencies and have strong strategic thinking to come up w/ paradigm shift solutions to critical design/validation challenges. Strong analysis, debugging skills, and creative in problem solving.

Qualifications:

A successful candidate will have proven experience demonstrating the following skills and behavioral traits:

• Strong analysis.
• Debugging skills.
• Creative in problem solving.

Minimum Qualifications

Minimum qualifications are required to be initially considered for this position.

Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.

• Bachelor's degree or advanced student in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
• 2 years of relevant logic design experience
• Advanced English level
• Costa Rican unrestricted work permit.

Preferred Qualifications:

Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
• or - 2+ years of experienced in:
  • System Verilog
  • Scripting (Python/Perl/Shell)
  • RTL simulators
  • Interactive debugger
  • RTL model build
  • Work experience with system Verilog or OVM or UVM or Object-Oriented Programming (OOP)
  • VLSI or Structural and Physical design flow/methodology experience.
  • Power management, IOSF, AHB, PCI express or any industry standard BUS protocol experience a plus.
• Testbench development.
• Work experience with system Verilog or OVM or UVM or Object-Oriented Programming (OOP)Formal Equivalence.
• Testing RTL model build Power
• Aware simulation Coverage
• Based random constraint simulation
• Power management, IOSF, AHB, PCI express or any industry standard BUS protocol experience a plusOVM / UVMScripting (Python/Perl/Shell)
• Interactive debugger

Job Type:

Experienced Hire

Shift:

Shift 1 (Costa Rica)

Primary Location:

Costa Rica, San Jose

Additional Locations:

Business group:

Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.