Job Description

Job Details:

About the Role

Do you have a software engineer's mindset and an obsession with finding the root cause of hard problems? Are you the kind of engineer who reads a spec for fun, debugs across layers without a map, and gets energised when nobody else knows what's wrong yet?

We're building the next generation of Neural Processing Unit (NPU) silicon at Intel's Leixlip site — and we're looking for someone to help us validate it works, find out when it doesn't, and figure out exactly why.

This is a post-silicon validation role. That means you will be working with real silicon, running tests on actual hardware, and debugging failures that nobody has seen before. On any given day you might be reading a microarchitecture spec, writing a C/C++ or python unit test, probing a power rail, or digging through kernel logs. You will collaborate directly with architecture and design teams across Intel.

Beyond functional validation, a significant part of this role involves power and performance characterisation and tuning. You will instrument silicon to understand how it behaves under real AI workloads — profiling power states, characterising frequency and voltage operating points, analysing performance counters, and working with architecture teams to close the gap between designed and measured behaviour. If you enjoy the intersection of empirical measurement, data analysis, and deep system understanding, this aspect of the role will be particularly rewarding.

We value how fast you learn over how much you already know. Our team is built from engineers with strong software foundations and broad full-stack intuition — from silicon architecture and physical design through to OS drivers and software stacks. If you've never done post-silicon validation before but you've always wanted to understand how hardware really works, this is your entry point.

What You'll Do

• Validate the functionality of next-generation AI silicon (NPU) across a broad range of workloads and scenarios
• Debug and root-cause failures encountered pre- and post-silicon — including intermittent, multi-domain, and hard-to-reproduce issues
• Design and develop validation infrastructure used across pre-silicon (simulation, emulation, FPGA) and post-silicon phases
• Characterise and profile silicon power and performance across a range of AI workloads — measuring, analysing, and interpreting results against architectural intent
• Support power and performance tuning efforts — working with architecture, design, and software teams to identify headroom, diagnose regressions, and validate optimisations on real hardware
• Read and interpret hardware architecture specifications to derive meaningful, targeted test cases
• Share findings, debug techniques, and best practices across the team and product lifecycle

Qualifications:

What We're Looking For (Required)

• Strong debug instinct — you work methodically, form hypotheses, isolate variables, and know how to rule things out efficiently
• Full-stack curiosity — you're comfortable holding a conversation from register-level hardware behaviour to OS scheduling and userspace software
• Learning agility — you pick up new technical domains quickly from documentation, specs, and first principles, with minimal hand-holding
• Software fundamentals — solid C/C++ development skills; you understand memory models, concurrency, and low-level behaviour
• Python scripting — for automation, data analysis, and test infrastructure
• Communication — you can explain a complex multi-layer bug clearly, in writing and verbally

What Will Make You Stand Out (Desired)

• OS-level driver experience on Linux or Windows — even if self-taught or project-based
• Familiarity with embedded toolchains: compilers, debuggers, build systems, revision control
• Exposure to FPGA, emulation platforms, or RTL simulation environments
• Experience with scripting languages (Bash, PowerShell, Tcl) for test automation
• Experience with performance profiling, benchmarking, or power measurement — in any domain (software profiling, embedded power optimisation, SoC characterisation, or equivalent)
• Any prior exposure to silicon validation, hardware bring-up, or embedded firmware — but this is genuinely not a prerequisite

Qualifications

• Bachelor's degree (NFQ Level 8) or Master's degree (NFQ Level 9) in Engineering, Computer Science, or a related field — or equivalent demonstrable experience

Why This Team?

We don't expect you to arrive knowing everything about silicon. We do expect you to be the kind of engineer who is genuinely excited to learn it. If the idea of being one of the first people to run code on a brand-new chip sounds more interesting than scary, we'd love to talk.

Our work spans functional validation, complex multi-domain debug, and hands-on power and performance characterisation on real AI silicon. Few roles give you this breadth of exposure across the full hardware-software stack — and the chance to directly influence both the correctness and the efficiency of next-generation NPU designs.

Job Type:

Experienced Hire

Shift:

Shift 1 (Ireland)

Primary Location:

Ireland, Leixlip

Additional Locations:

Business group:

Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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