Job Description

Key Responsibilities:

• Work closely with a team of design and fabrication scientists to lay out masks for next generation ion traps
• Collaborate with a cross-functional team to ensure designs are consistent with good layout practices
• Work with our foundries to ensure design and tape out is consistent with their PDKs and/or best practices

YOU MUST HAVE:

• Bachelor’s Degree minimum
• Minimum 5 years' experience doing IC or MEMS layout using Cadence Virtuoso, from initial conception through tape out
• Due to Contractual requirements, must be a U.S. Person. defined as, U.S. citizen permanent resident or green card holder, workers granted asylum or refugee status
• Due to national security requirements imposed by the U.S. Government, candidates for this position must not be a People's Republic of China national or Russian national unless the candidate is also a U.S. citizen.

WE VALUE:

• Bachelor’s degree in electrical engineering or physics
• 5 years’ experience with integrated circuit layout and simulation in Cadence Virtuoso, including inserting, modifying and using a PDK in Cadence
• 5 years’ experience taping out layouts and delivering to mask shops
• Experience laying out masks for external (i.e., non-captive) foundries
• Experience using Linux OS
• Familiarity with SKILL language script
• 2 years’ experience with MEMS layout tools and techniques such as Tanner L-Edit, K-Layout or similar
• Experience with layout of photonics components
• Familiarity with auto-routing in layout
• Experience working in a cross-functional, R&D team environment